The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BI...The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.展开更多
针对超高速率的光传送网络(Optical Transport Network,OTN)数据信号,在研究光传送网络帧结构的基础上,提出了一种适合高速率、大位宽的成帧器处理电路,将48比特的FAS信号分为两部分进行比较,第一部分为64个24比特比较器,第二部分为一...针对超高速率的光传送网络(Optical Transport Network,OTN)数据信号,在研究光传送网络帧结构的基础上,提出了一种适合高速率、大位宽的成帧器处理电路,将48比特的FAS信号分为两部分进行比较,第一部分为64个24比特比较器,第二部分为一个24比特比较器。将电路的规模降低了一半,提高了电路的处理速率。通过软件仿真后,使用综合工具综合的结果显示,电路处理速率可达到235.74MHz。展开更多
文摘The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.
文摘针对超高速率的光传送网络(Optical Transport Network,OTN)数据信号,在研究光传送网络帧结构的基础上,提出了一种适合高速率、大位宽的成帧器处理电路,将48比特的FAS信号分为两部分进行比较,第一部分为64个24比特比较器,第二部分为一个24比特比较器。将电路的规模降低了一半,提高了电路的处理速率。通过软件仿真后,使用综合工具综合的结果显示,电路处理速率可达到235.74MHz。
