This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface,which is compliant with many serial communication specifications such ...This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface,which is compliant with many serial communication specifications such as USB2.0,PCI-E2.0 and Rapid 10.The low and high frequency loops are merged to decrease the effect of delay between the two paths,in addition,the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain.The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces,which brings as much as 25 dB loss.The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation.In addition,AC coupling is adopted to suppress the common input from the forward stage.A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology.The actual area is 0.6×0.57 mm;and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss.The overall power dissipation is approximately 23.4 mW.展开更多
基金Project supported by the National Key Program of China(No.2009ZX03007-002-03)
文摘This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface,which is compliant with many serial communication specifications such as USB2.0,PCI-E2.0 and Rapid 10.The low and high frequency loops are merged to decrease the effect of delay between the two paths,in addition,the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain.The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces,which brings as much as 25 dB loss.The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation.In addition,AC coupling is adopted to suppress the common input from the forward stage.A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology.The actual area is 0.6×0.57 mm;and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss.The overall power dissipation is approximately 23.4 mW.
