Electrical Impedance Tomography(EIT)as a non-invasive of electrical conductivity imaging method commonly employs the stationary-coefficient based filters(such as FFT)in order to remove the noise signal.In the practica...Electrical Impedance Tomography(EIT)as a non-invasive of electrical conductivity imaging method commonly employs the stationary-coefficient based filters(such as FFT)in order to remove the noise signal.In the practical applications,the stationary-coefficient based filters fail to remove the time-varying random noise which leads to the lack of impedance measurement sensitivity.In this paper,the implementation of adaptive noise cancellation(ANC)algorithms which are Least Mean Square(LMS)and Normalized Least Mean Square(NLMS)filters onto Field Programmable Gate Array(FPGA)-based EIT system is proposed in order to eliminate the time-varying random noise signal.The proposed method was evaluated through experimental studies with biomaterial phantom.The reconstructed EIT images with NLMS is better than the images with LMS by amplitude response AR=12.5%,position error PE=200%,resolution RES=33%,and shape deformation SD=66%.Moreover,the Analog-to-Digital Converter(ADC)performances of power spectral density(PSD)and the effective number of bit ENOB with NLMS is higher than the performances with LMS by SI=5.7%and ENOB=15.4%.The results showed that implementing ANC algorithms onto FPGA-based EIT system shows significantly more accurate image reconstruction as compared without ANC algorithms implementation.展开更多
A novel FPGA-based pulse pile-up rejection method for single photon imaging detectors is reported. Tile method is easy to implement in FPGAs for real-time data processing. The rejection principle and entire design are...A novel FPGA-based pulse pile-up rejection method for single photon imaging detectors is reported. Tile method is easy to implement in FPGAs for real-time data processing. The rejection principle and entire design are introduced in detail. The photon counting imaging detector comprises a micro-channel plate （MCP） stack, and a wedge and strip anode （WSA）. The resolution mask pattern in front of the MCP can be reconstructed after data processing in the FPGA. For high count rates, the rejection design can effectively reduce the impact of the pulse pile-up on the image. The resolution can reach up to 140μm. The pulse pile-up rejection design can also be applied to high-energy physics and particle detection.展开更多
The high-speed computational performance is gained at the cost of huge hardware resource,which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use.To solve the p...The high-speed computational performance is gained at the cost of huge hardware resource,which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use.To solve the problem,a novel method for designing the field programmable gate array(FPGA)-based non-uniform rational B-spline(NURBS) interpolator and motion controller,which adopts the embedded multiprocessor technique,is proposed in this study.The hardware and software design for the multiprocessor,one of which is for NURBS interpolation and the other for position servo control,is presented.Performance analysis and experiments on an X-Y table are carried out,hardware cost as well as consuming time for interpolation and motion control is compared with the existing methods.The experimental and comparing results indicate that,compared with the existing methods,the proposed method can reduce the hardware cost by 97.5% using higher-accuracy interpolation algorithm within the period of 0.5 ms.A method which ensures the real-time performance and interpolation accuracy,and reduces the hardware cost significantly is proposed,and it’s practical in the use of industrial application.展开更多
基金he International Research Fellow of Japan Society for the Promotion of Science(Graduate School of Science and Engineering,Chiba University)and JSPS KAKENHI Grant Number JP18F18060.
文摘Electrical Impedance Tomography(EIT)as a non-invasive of electrical conductivity imaging method commonly employs the stationary-coefficient based filters(such as FFT)in order to remove the noise signal.In the practical applications,the stationary-coefficient based filters fail to remove the time-varying random noise which leads to the lack of impedance measurement sensitivity.In this paper,the implementation of adaptive noise cancellation(ANC)algorithms which are Least Mean Square(LMS)and Normalized Least Mean Square(NLMS)filters onto Field Programmable Gate Array(FPGA)-based EIT system is proposed in order to eliminate the time-varying random noise signal.The proposed method was evaluated through experimental studies with biomaterial phantom.The reconstructed EIT images with NLMS is better than the images with LMS by amplitude response AR=12.5%,position error PE=200%,resolution RES=33%,and shape deformation SD=66%.Moreover,the Analog-to-Digital Converter(ADC)performances of power spectral density(PSD)and the effective number of bit ENOB with NLMS is higher than the performances with LMS by SI=5.7%and ENOB=15.4%.The results showed that implementing ANC algorithms onto FPGA-based EIT system shows significantly more accurate image reconstruction as compared without ANC algorithms implementation.
基金Supported by the National Natural Science Foundation of China under Grant No 11375179
文摘A novel FPGA-based pulse pile-up rejection method for single photon imaging detectors is reported. Tile method is easy to implement in FPGAs for real-time data processing. The rejection principle and entire design are introduced in detail. The photon counting imaging detector comprises a micro-channel plate （MCP） stack, and a wedge and strip anode （WSA）. The resolution mask pattern in front of the MCP can be reconstructed after data processing in the FPGA. For high count rates, the rejection design can effectively reduce the impact of the pulse pile-up on the image. The resolution can reach up to 140μm. The pulse pile-up rejection design can also be applied to high-energy physics and particle detection.
基金supported by National Key Basic Research Program of China(973 ProgramGrant No.2011CB706804)+1 种基金Shanghai Municipal Science and Technology Commission of China(Grant No.11QH1401400)Research Project of State Key Laboratory of Mechanical System & Vibration of China(Grant No.MSVMS201102)
文摘The high-speed computational performance is gained at the cost of huge hardware resource,which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use.To solve the problem,a novel method for designing the field programmable gate array(FPGA)-based non-uniform rational B-spline(NURBS) interpolator and motion controller,which adopts the embedded multiprocessor technique,is proposed in this study.The hardware and software design for the multiprocessor,one of which is for NURBS interpolation and the other for position servo control,is presented.Performance analysis and experiments on an X-Y table are carried out,hardware cost as well as consuming time for interpolation and motion control is compared with the existing methods.The experimental and comparing results indicate that,compared with the existing methods,the proposed method can reduce the hardware cost by 97.5% using higher-accuracy interpolation algorithm within the period of 0.5 ms.A method which ensures the real-time performance and interpolation accuracy,and reduces the hardware cost significantly is proposed,and it’s practical in the use of industrial application.
