In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchao...In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchaos. The hyperchaotic nature is verified theoretically by using the bifurcation analysis and demonstrated experimentally by the implementation of an analogue electronic circuit. Moreover, the Field Programmable Gate Array （FPGA） technology is applied to implementing a continuous system in a digital form by using a chip of Altera Cyclone II EP2C35F484C8. The digital sequence generated from the FPGA device is observed in our experimental setup.展开更多
In this paper, the structure of a new chaotic bitwise dynamical system （CBDS） is described. Compared to our previous research work, it uses various random bitwise operations instead of only one. The chaotic behavior...In this paper, the structure of a new chaotic bitwise dynamical system （CBDS） is described. Compared to our previous research work, it uses various random bitwise operations instead of only one. The chaotic behavior of CBDS is mathemat- ically proven according to the Devaney＇s definition, and its statistical properties are verified both for uniformity and by a comprehensive, reputed and stringent battery of tests called TestU01. Furthermore, a systematic methodology developing the parallel computations is proposed for FPGA platform-based realization of this CBDS. Experiments finally validate the proposed systematic methodology.展开更多
An improved heterogeneous dual memristive circuit(DMC)is proposed based on Chua's circuit,which shows good symmetry and multistablility.For the difficulty in controlling the initial conditions,which restricts the ...An improved heterogeneous dual memristive circuit(DMC)is proposed based on Chua's circuit,which shows good symmetry and multistablility.For the difficulty in controlling the initial conditions,which restricts the engineering applications,the 3 rd-order model(3 OM)in flux-charge domain is derived from the 5 th-order model(5 OM)in volt-ampere domain by using the flux-charge analysis method(FCAM).The consistence of symmetry and multistability before and after dimensionality decreasing is meticulously investigated via bifurcation diagram,Lyapunov exponents,and especially attraction basins.The comparative analysis validates the effectiveness of reduction model and improves the controllability of the circuit.To avoid the noise in the analog circuit,a field-programmable gate array(FPGA)is utilized to realize the reduction model,which is rarely reported and valuable for relevant research and application.展开更多
It is necessary to know the status of adhesion conditions between wheel and rail for efficient accelerating and decelerating of railroad vehicle.The proper estimation of adhesion conditions and their real-time impleme...It is necessary to know the status of adhesion conditions between wheel and rail for efficient accelerating and decelerating of railroad vehicle.The proper estimation of adhesion conditions and their real-time implementation is considered a challenge for scholars.In this paper,the development of simulation model of extended Kalman filter(EKF)in MATLAB/Simulink is presented to estimate various railway wheelset parameters in different contact conditions of track.Due to concurrent in nature,the Xilinx®System-on-Chip Zynq Field Programmable Gate Array(FPGA)device is chosen to check the onboard estimation ofwheel-rail interaction parameters by using the National Instruments(NI)myRIO®development board.The NImyRIO®development board is flexible to deal with nonlinearities,uncertain changes,and fastchanging dynamics in real-time occurring in wheel-rail contact conditions during vehicle operation.The simulated dataset of the railway nonlinear wheelsetmodel is tested on FPGA-based EKF with different track conditions and with accelerating and decelerating operations of the vehicle.The proposed model-based estimation of railway wheelset parameters is synthesized on FPGA and its simulation is carried out for functional verification on FPGA.The obtained simulation results are aligned with the simulation results obtained through MATLAB.To the best of our knowledge,this is the first time study that presents the implementation of a model-based estimation of railway wheelset parameters on FPGA and its functional verification.The functional behavior of the FPGA-based estimator shows that these results are the addition of current knowledge in the field of the railway.展开更多
In an advancement of communication field, wireless technology plays a predominant role in data transmission. In the timeline of wireless domain, Wi-Fi, Bluetooth, zigbee etc are some of the standards, which are being ...In an advancement of communication field, wireless technology plays a predominant role in data transmission. In the timeline of wireless domain, Wi-Fi, Bluetooth, zigbee etc are some of the standards, which are being used in today’s wireless medium. In addition, the WiMax is introduced by IEEE in IEEE 802.16 for long distance communication, specifically 802.16e standard for mobile WiMax. It is an acronym of Worldwide Interoperability for Microwave Access. It is to be deliver wireless transmission with high quality of service in a secured environment. Since, security becomes dominant design aspect of every communication, a new technique has been proposed in wireless environment. Privacy across the network and access control management is the goal in the predominant aspects in the WiMax protocol. Especially, MAC sub layer should be evaluated in the security architecture. It has been proposed on cryptography algorithm AES that require high cost. Under this scenario, we present the optimized AES 128 bit counter mode security algorithm for MAC layer of 802.16e standards. To design a efficient MAC layer, we adopt the modification of security layers data handling process. As per the efficient design strategy, the power and speed are the dominant factors in mobile device. Since we concentrate mobile WiMax, efficient design is needed for MAC Security layer. Our proposed model incorporates the modification of AES algorithm. The design has been implemented in Xilinx virtex5 device and power has been analyzed using XPower analyzer. This proposed system consumes 41% less power compare to existing system.展开更多
随着数字音源的普及,数模转换器(Digital to Analog Converter, DAC)成为音频设备中不可或缺的元件,其精度往往决定着整个系统的信号保真度。基于此,利用噪声整形技术对用于高精度音频DAC的Sigma-Delta调制器进行设计和现场可编程门阵列...随着数字音源的普及,数模转换器(Digital to Analog Converter, DAC)成为音频设备中不可或缺的元件,其精度往往决定着整个系统的信号保真度。基于此,利用噪声整形技术对用于高精度音频DAC的Sigma-Delta调制器进行设计和现场可编程门阵列(Field Programmable Gate Array, FPGA)实现。通过搭建测试系统,测试结果表明,所设计的Sigma-Delta调制器在输入信号为1 411.2 kHz采样频率、1 kHz频率、0 dBFS(Full Scale)幅度的正弦信号条件下,其输出信噪比(Signal to Noise Ratio, SNR)可达107.4 dB;当输入信号频率在音频频带内时(输入信号幅度为0dBFS),其输出SNR稳定保持在104 dB以上;并可用于WAV音乐播放器中。展开更多
数字签名算法对于网络安全基础设施有至关重要的作用,目前的数字签名方案大多是基于Rivest-Shamir-Adleman(RSA)和椭圆曲线密码学(ECC)实现的.随着量子计算技术的快速发展,基于传统的公钥密码体系的数字签名方案将面临安全性风险,研究...数字签名算法对于网络安全基础设施有至关重要的作用,目前的数字签名方案大多是基于Rivest-Shamir-Adleman(RSA)和椭圆曲线密码学(ECC)实现的.随着量子计算技术的快速发展,基于传统的公钥密码体系的数字签名方案将面临安全性风险,研究和部署能够抵抗量子攻击的新型密码方案成为重要的研究方向.经过多轮评估分析,美国国家标准研究院(National Institute of Standards and Technology,NIST)于2024年8月公布了后量子数字签名标准方案ML-DSA,其核心算法是Dilithium.针对格基数字签名算法Dilithium高维多项式矩阵运算的特点,基于FPGA平台提出了多种优化实现方法,具体包括可配置参数的多功能脉动阵列运算单元、专用型多项式并行采样模块、针对多参数集的可重构存储单元设计、针对复杂多模块的高并行度时序状态机,旨在突破性能瓶颈以实现更高的签名运算效率,并最终实现了可同时支持3种安全等级的数字签名硬件架构.该设计方案在Xilinx Artix-7 FPGA平台上进行了实际的部署和运行,并且和已有的同类型工作进行了对比.结果表明,与最新的文献相比,该设计方案在3种安全等级下的签名运算效率分别提升了7.4、8.3和5.6倍,为抗量子安全的数字签名运算服务提供了性能基础,并且对于推进格密码方案的工程化和实用化进程提供了一定的借鉴意义和参考价值.展开更多
An autonomous five-dimensional(5D)system with offset boosting is constructed by modifying the well-known three-dimensional autonomous Liu and Chen system.Equilibrium points of the proposed autonomous 5D system are fou...An autonomous five-dimensional(5D)system with offset boosting is constructed by modifying the well-known three-dimensional autonomous Liu and Chen system.Equilibrium points of the proposed autonomous 5D system are found and its stability is analyzed.The proposed system includes Hopf bifurcation,periodic attractors,quasi-periodic attractors,a one-scroll chaotic attractor,a double-scroll chaotic attractor,coexisting attractors,the bistability phenomenon,offset boosting with partial amplitude control,reverse period-doubling,and an intermittency route to chaos.Using a field programmable gate array(FPGA),the proposed autonomous 5D system is implemented and the phase portraits are presented to check the numerical simulation results.The chaotic attractors and coexistence of the attractors generated by the FPGA implementation of the proposed system have good qualitative agreement with those found during the numerical simulation.Finally,a sound data encryption and communication system based on the proposed autonomous 5D chaotic system is designed and illustrated through a numerical example.展开更多
该文基于现场可编程门阵列(field-programmable gate array,FPGA),为永磁同步电机驱动提出一种扩张控制集模型预测电流控制策略(model predictive current control,MPCC)。由于在每个控制周期内只有8个基本电压矢量可供选择,传统有限控...该文基于现场可编程门阵列(field-programmable gate array,FPGA),为永磁同步电机驱动提出一种扩张控制集模型预测电流控制策略(model predictive current control,MPCC)。由于在每个控制周期内只有8个基本电压矢量可供选择,传统有限控制集模型预测电流控制(finite control set MPCC,FCS-MPCC)稳态性能较低。为此,文中采用具有818个可选矢量的ECS来实现更精细的电压输出。为减轻因电压矢量大幅增加而带来的计算负担,设计一种简化的最优矢量搜索策略,且可推广用于其他多目标成本函数。基于算法固有并行性,将所提ECS-MPCC方法在FPGA中进行实现,使电流环总控制时间缩短至0.59μs,从而可以消除计算延迟,提高电流环动态性能。最后,通过仿真和实验,验证所提ECS-MPCC策略的有效性。实验结果表明,与传统FCS-MPCC相比,ECS-MPCC的相电流总谐波失真降低77%。展开更多
This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcatio...This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcation diagram, basic dynamics have been analyzed. The hardware implementation of the system is based on Field Programmable Gate Array (FPGA). It is shown that the experimental results are identical with numerical simulations, and the chaotic trajectories are much more complex.展开更多
Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for...Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.展开更多
基金Project supported by the Natural Science Foundation of Zhejiang Province, China (Grant No Y105175) the Science investigation Foundation of Hangzhou Dianzi University, China (Grant No KYS051505010)
文摘In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchaos. The hyperchaotic nature is verified theoretically by using the bifurcation analysis and demonstrated experimentally by the implementation of an analogue electronic circuit. Moreover, the Field Programmable Gate Array （FPGA） technology is applied to implementing a continuous system in a digital form by using a chip of Altera Cyclone II EP2C35F484C8. The digital sequence generated from the FPGA device is observed in our experimental setup.
基金Project supported by China Postdoctoral Science Foundation(Grant No.2014M552175)the Scientific Research Foundation for the Returned Overseas Chinese Scholars,Chinese Education Ministry+1 种基金the National Natural Science Foundation of China(Grant No.61172023)the Specialized Research Foundation of Doctoral Subjects of Chinese Education Ministry(Grant No.20114420110003)
文摘In this paper, the structure of a new chaotic bitwise dynamical system （CBDS） is described. Compared to our previous research work, it uses various random bitwise operations instead of only one. The chaotic behavior of CBDS is mathemat- ically proven according to the Devaney＇s definition, and its statistical properties are verified both for uniformity and by a comprehensive, reputed and stringent battery of tests called TestU01. Furthermore, a systematic methodology developing the parallel computations is proposed for FPGA platform-based realization of this CBDS. Experiments finally validate the proposed systematic methodology.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61971228 and 61871230)the Natural Science Foundations of Jiangsu Higher Education Institutions,China(Grant No.19KJB520042)the Postgraduate Research&Practice Innovation Program of Jiangsu Province,China(Grant No.SJCX210564)。
文摘An improved heterogeneous dual memristive circuit(DMC)is proposed based on Chua's circuit,which shows good symmetry and multistablility.For the difficulty in controlling the initial conditions,which restricts the engineering applications,the 3 rd-order model(3 OM)in flux-charge domain is derived from the 5 th-order model(5 OM)in volt-ampere domain by using the flux-charge analysis method(FCAM).The consistence of symmetry and multistability before and after dimensionality decreasing is meticulously investigated via bifurcation diagram,Lyapunov exponents,and especially attraction basins.The comparative analysis validates the effectiveness of reduction model and improves the controllability of the circuit.To avoid the noise in the analog circuit,a field-programmable gate array(FPGA)is utilized to realize the reduction model,which is rarely reported and valuable for relevant research and application.
文摘It is necessary to know the status of adhesion conditions between wheel and rail for efficient accelerating and decelerating of railroad vehicle.The proper estimation of adhesion conditions and their real-time implementation is considered a challenge for scholars.In this paper,the development of simulation model of extended Kalman filter(EKF)in MATLAB/Simulink is presented to estimate various railway wheelset parameters in different contact conditions of track.Due to concurrent in nature,the Xilinx®System-on-Chip Zynq Field Programmable Gate Array(FPGA)device is chosen to check the onboard estimation ofwheel-rail interaction parameters by using the National Instruments(NI)myRIO®development board.The NImyRIO®development board is flexible to deal with nonlinearities,uncertain changes,and fastchanging dynamics in real-time occurring in wheel-rail contact conditions during vehicle operation.The simulated dataset of the railway nonlinear wheelsetmodel is tested on FPGA-based EKF with different track conditions and with accelerating and decelerating operations of the vehicle.The proposed model-based estimation of railway wheelset parameters is synthesized on FPGA and its simulation is carried out for functional verification on FPGA.The obtained simulation results are aligned with the simulation results obtained through MATLAB.To the best of our knowledge,this is the first time study that presents the implementation of a model-based estimation of railway wheelset parameters on FPGA and its functional verification.The functional behavior of the FPGA-based estimator shows that these results are the addition of current knowledge in the field of the railway.
文摘In an advancement of communication field, wireless technology plays a predominant role in data transmission. In the timeline of wireless domain, Wi-Fi, Bluetooth, zigbee etc are some of the standards, which are being used in today’s wireless medium. In addition, the WiMax is introduced by IEEE in IEEE 802.16 for long distance communication, specifically 802.16e standard for mobile WiMax. It is an acronym of Worldwide Interoperability for Microwave Access. It is to be deliver wireless transmission with high quality of service in a secured environment. Since, security becomes dominant design aspect of every communication, a new technique has been proposed in wireless environment. Privacy across the network and access control management is the goal in the predominant aspects in the WiMax protocol. Especially, MAC sub layer should be evaluated in the security architecture. It has been proposed on cryptography algorithm AES that require high cost. Under this scenario, we present the optimized AES 128 bit counter mode security algorithm for MAC layer of 802.16e standards. To design a efficient MAC layer, we adopt the modification of security layers data handling process. As per the efficient design strategy, the power and speed are the dominant factors in mobile device. Since we concentrate mobile WiMax, efficient design is needed for MAC Security layer. Our proposed model incorporates the modification of AES algorithm. The design has been implemented in Xilinx virtex5 device and power has been analyzed using XPower analyzer. This proposed system consumes 41% less power compare to existing system.
文摘数字签名算法对于网络安全基础设施有至关重要的作用,目前的数字签名方案大多是基于Rivest-Shamir-Adleman(RSA)和椭圆曲线密码学(ECC)实现的.随着量子计算技术的快速发展,基于传统的公钥密码体系的数字签名方案将面临安全性风险,研究和部署能够抵抗量子攻击的新型密码方案成为重要的研究方向.经过多轮评估分析,美国国家标准研究院(National Institute of Standards and Technology,NIST)于2024年8月公布了后量子数字签名标准方案ML-DSA,其核心算法是Dilithium.针对格基数字签名算法Dilithium高维多项式矩阵运算的特点,基于FPGA平台提出了多种优化实现方法,具体包括可配置参数的多功能脉动阵列运算单元、专用型多项式并行采样模块、针对多参数集的可重构存储单元设计、针对复杂多模块的高并行度时序状态机,旨在突破性能瓶颈以实现更高的签名运算效率,并最终实现了可同时支持3种安全等级的数字签名硬件架构.该设计方案在Xilinx Artix-7 FPGA平台上进行了实际的部署和运行,并且和已有的同类型工作进行了对比.结果表明,与最新的文献相比,该设计方案在3种安全等级下的签名运算效率分别提升了7.4、8.3和5.6倍,为抗量子安全的数字签名运算服务提供了性能基础,并且对于推进格密码方案的工程化和实用化进程提供了一定的借鉴意义和参考价值.
文摘An autonomous five-dimensional(5D)system with offset boosting is constructed by modifying the well-known three-dimensional autonomous Liu and Chen system.Equilibrium points of the proposed autonomous 5D system are found and its stability is analyzed.The proposed system includes Hopf bifurcation,periodic attractors,quasi-periodic attractors,a one-scroll chaotic attractor,a double-scroll chaotic attractor,coexisting attractors,the bistability phenomenon,offset boosting with partial amplitude control,reverse period-doubling,and an intermittency route to chaos.Using a field programmable gate array(FPGA),the proposed autonomous 5D system is implemented and the phase portraits are presented to check the numerical simulation results.The chaotic attractors and coexistence of the attractors generated by the FPGA implementation of the proposed system have good qualitative agreement with those found during the numerical simulation.Finally,a sound data encryption and communication system based on the proposed autonomous 5D chaotic system is designed and illustrated through a numerical example.
文摘该文基于现场可编程门阵列(field-programmable gate array,FPGA),为永磁同步电机驱动提出一种扩张控制集模型预测电流控制策略(model predictive current control,MPCC)。由于在每个控制周期内只有8个基本电压矢量可供选择,传统有限控制集模型预测电流控制(finite control set MPCC,FCS-MPCC)稳态性能较低。为此,文中采用具有818个可选矢量的ECS来实现更精细的电压输出。为减轻因电压矢量大幅增加而带来的计算负担,设计一种简化的最优矢量搜索策略,且可推广用于其他多目标成本函数。基于算法固有并行性,将所提ECS-MPCC方法在FPGA中进行实现,使电流环总控制时间缩短至0.59μs,从而可以消除计算延迟,提高电流环动态性能。最后,通过仿真和实验,验证所提ECS-MPCC策略的有效性。实验结果表明,与传统FCS-MPCC相比,ECS-MPCC的相电流总谐波失真降低77%。
文摘This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcation diagram, basic dynamics have been analyzed. The hardware implementation of the system is based on Field Programmable Gate Array (FPGA). It is shown that the experimental results are identical with numerical simulations, and the chaotic trajectories are much more complex.
基金financially supported by the National Council for Scientific and Technological Development(CNPq,Brazil),Swedish-Brazilian Research and Innovation Centre(CISB),and Saab AB under Grant No.CNPq:200053/2022-1the National Council for Scientific and Technological Development(CNPq,Brazil)under Grants No.CNPq:312924/2017-8 and No.CNPq:314660/2020-8.
文摘Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.
