By using the theory of clipping voltage-switches, two kinds of master/slave nMOS quaternary flip-flops are designed. These flip-flops have the capability of two-input presetting and double-rail complementary outputs. ...By using the theory of clipping voltage-switches, two kinds of master/slave nMOS quaternary flip-flops are designed. These flip-flops have the capability of two-input presetting and double-rail complementary outputs. It is shown that these flip-flops are effectively suitable to design nMOS quaternary sequential circuits by designing two examples of hexadecimal up-counter and decimal up-counter.展开更多
A kind of structure and a design method using transmission voltage-switch theory for pulse-triggered flip-flops were proposed,which are suitable for all kinds of pulse-triggered flip-flops and no extra techniques are ...A kind of structure and a design method using transmission voltage-switch theory for pulse-triggered flip-flops were proposed,which are suitable for all kinds of pulse-triggered flip-flops and no extra techniques are needed to eliminate the switching activities of internal nodes.Based on the proposed structure and design technique,two pulsed flip-flops were implemented and simulated.The proposed pulsed flip-flops have simple circuit structures.HSPICE simulation shows that the proposed pulsed D flip-flop outperforms the conventional pulsed D flip-flop by 17.2% in delay and 30.1% in power-delay-product(PDP) and the proposed pulsed JK flip-flop has low power and small PDP compared with pulsed D pulsed flip-flops,confirming that the proposed structure and design technique are simple and practical.展开更多
In nanoscale technology, transistor aging is one of the most critical problems that impact on the reliability of circuits. Aging sensor is a good online way to detect the circuit aging, which performs during the opera...In nanoscale technology, transistor aging is one of the most critical problems that impact on the reliability of circuits. Aging sensor is a good online way to detect the circuit aging, which performs during the operating time with no influence of the normal operation of circuits. In this paper, a Dou- ble-edge-triggered Detection Sensor for circuit Aging （DSDA） is proposed, which employs data signal of logic circuits as its clock to control the sampling process. The simulation is done by Hspice using 45 nm technology. The results show that this technique is not case of the detection precision is more than 80% under aging fault effectively with the 8% power cost and 30% sensitive to the process variations. The worst the different process variations. It can detect performance cost.展开更多
This research deals with the oscillation mechanism of a flip-flop jet nozzle with a connecting tube, based on the measurements of pressures and velocities in the connecting tube and inside the nozzle. The measurements...This research deals with the oscillation mechanism of a flip-flop jet nozzle with a connecting tube, based on the measurements of pressures and velocities in the connecting tube and inside the nozzle. The measurements are carried out varying: 1) the inside diameter d of the connecting tube;2) the length L of the connecting tube and 3) the jet velocity VPN from a primary-nozzle exit. We assume that the jet switches when a time integral reaches a certain value. At first, as the time integral, we introduce the accumulated flow work of pressure, namely, the time integral of mass flux through a connecting tube into the jet-reattaching wall from the opposite jet-un-reattaching wall. Under the assumption, the trace of pressure difference between both the ends of the connecting tube is simply modeled on the basis of measurements, and the flow velocity in the connecting tube is computed as incompressible flow. Second, in order to discuss the physics of the accumulated flow work further, we conduct another experiment in single-port control where the inflow from the control port on the jet-reattaching wall is forcibly controlled and the other control port on the opposite jet-un-reattaching wall is sealed, instead of the experiment in regular jet’s oscillation using the ordinary nozzle with two control ports in connection. As a result, it is found that the accumulated flow work is adequate to determine the dominant jet- oscillation frequency. In the experiment in single-port control, the accumulated flow work of the inflow until the jet’s switching well agrees with that in regular jet’s oscillation using the ordinary nozzle.展开更多
Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories ...Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory （DRAM） with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops （NVFFs） seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.展开更多
According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ter...According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ternary sequential circuits are implemented by usingarray of universal-logic-modules,U_hs.展开更多
As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of th...As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of the entire circuit system. Understanding the factors that influence the SET sensitivity of the CDN is crucial to achieving radiation hardening of the CDN and realizing the design of highly reliable ICs. In this paper, the influences of different sequential elements(D-flip-flops and D-latches, the two most commonly used sequential elements in modern synchronous digital systems) on the SET susceptibility of the CDN were quantitatively studied. Electrical simulation and heavy ion experiment results reveal that the CDN-SET-induced incorrect latching is much more likely to occur in DFF and DFF-based designs. This can supply guidelines for the design of IC with high reliability.展开更多
The design of ternary edge-triggered JKL-type flip-flop is proposed.The computersimulation and the test in experimental circuit made up with TTL gate show this flip-flop has theexpected logic functions.
The flow visualization work with the aid of PIV and Piezometer deals with flip-flop flow around diamond-shaped cylinder bundle revised with concavities on both bundle walls. It is disclosed that 1) the concavity const...The flow visualization work with the aid of PIV and Piezometer deals with flip-flop flow around diamond-shaped cylinder bundle revised with concavities on both bundle walls. It is disclosed that 1) the concavity constructed on both side-walls of a diamond cylinder induces a substantial change in the flow patterns in the exit jet-stream field and jet- stream dispersion, 2) pressure characteristics are quantitatively measured in a diverging-flow region in diamond cylinder bundles with concavityand in its downstream region, and 3) flip-flop flow occurs in the flow passages and its occurrence condition is obtained.展开更多
Variable supply voltage-clustered voltage scaling （VS-CVS） scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops （LCFFs） are ...Variable supply voltage-clustered voltage scaling （VS-CVS） scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops （LCFFs） are key elements in the CVS scheme. In this paper, a new explicit-pulsed double-edge triggered level converting flip-flop （nEP-DET-LCFF） is proposed, which employs double-edge triggering technique, dynamic structure, explicit pulse generator, conditional discharge technique and proper arrangement of stacked nMOS transistors to efficiently perform latching and level converting functions simultaneously. The proposed nEP-DET-LCFF combines merits of both conventional explicit-LCFFs and implicit-LCFFs. Simulation shows the proposed nEP-DET-LCFF has improvement of 19.2% -46% in delay, and 19.4% - 52.9% in power-delay product （PDP） as compared with the published LCFFs.展开更多
A new all optical flip-flop based on a 3-sections nonlinear semiconductor DFB laser structure is proposed and simulated. The operation of the device does not require a holding beam. Electrical current injection into a...A new all optical flip-flop based on a 3-sections nonlinear semiconductor DFB laser structure is proposed and simulated. The operation of the device does not require a holding beam. Electrical current injection into an active layer provides optical gain to the laser mode. The wave-guiding layer consists of a linear grating section centered between 2 detuned nonlinear grating sections. The average refractive index in the nonlinear sections is slightly higher than the refractive index of the middle section. A negative nonlinear refractive index coefficient exists along the nonlinear sections. In the “OFF” state, the DFB structure does not provide enough optical feedback to lase due to the detuned sections. At high light intensity in structure, “ON” state, detuning decreases and the DFB structure allows for a laser mode that sustains the decrease in detuning to exist. The nonlinearity is provided by direct photon absorption at the Urbach tail. Numerical simulations using GPGPU computing show nanoseconds transition times between “OFF” and “ON” states.展开更多
A new design for an all optical flip flop is introduced. It is based on a nonlinear Distributed Bragg Reflector (DBR) semiconductor laser structure. The device does not require a holding beam. An optical gain medium c...A new design for an all optical flip flop is introduced. It is based on a nonlinear Distributed Bragg Reflector (DBR) semiconductor laser structure. The device does not require a holding beam. An optical gain medium confined between 2 Bragg reflectors forms the device. One of the Bragg reflectors is detuned from the other by making its average refractive index slightly higher, and it has a negative nonlinear coefficient that is due to direct absorption at Urbach tail. At low light intensity in the structure, the detuned Bragg reflector does not provide optical feedback to start a laser mode. An optical pulse injected to the structure reduces the detuning of the nonlinear Bragg reflector and a laser mode builds up. The device is reset by detuning the second Bragg reflector optically by an optical pulse that generates electron-hole pairs by direct absorption. A mathematical model of the device is introduced. The model is solved numerically in time domain using a general purpose graphics processing unit (GPGPU) to increase accuracy and to reduce the computation time. The switching dynamics of the device are in nanosecond time scale. The device could be used for all optical data packet switching/routing.展开更多
A new all-optical flip-flop based on a nonlinear Distributed feedback (DFB) structure is proposed. The device does not require a holding beam. A nonlinear part of the grating is detuned from the remaining part of the ...A new all-optical flip-flop based on a nonlinear Distributed feedback (DFB) structure is proposed. The device does not require a holding beam. A nonlinear part of the grating is detuned from the remaining part of the grating and has negative nonlinear coefficient. Optical gain is provided by an injected electrical current into an active layer. In the OFF state, due to the detuned section, no laser light is generated in the device. An injected optical pulse reduces the detuning of the nonlinear section, and the optical feedback provided by the DFB structure generates a laser light in the structure that sustains the change in the detuned section. The device is switched “OFF” by detuning another section of the grating by a Reset pulse. The Reset pulse reduces the refractive index of that section by the generation of electron-hole pairs. The Reset pulse wavelength is adjusted such that the optical gain provided by the active layer at that wavelength is zero. The Reset pulse is prevented from reaching the nonlinear detuned section by introducing an optical absorber in the laser cavity to attenuate the pulse. The device is simulated in time domain using General Purpose Graphics Processing Unit (GPGPU) computing. Set-Reset operations are in nanosecond time scale.展开更多
Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip...Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.展开更多
功耗攻击是一种通过统计电路的功耗信息得到敏感数据信息的攻击手段。作为电路的重要组成单元,触发器的抗功耗攻击水平与电路的安全性能息息相关,为此提出一种抗功耗攻击型触发器。通过引入“预充电-求值-放电”三阶段逻辑,提出了改进...功耗攻击是一种通过统计电路的功耗信息得到敏感数据信息的攻击手段。作为电路的重要组成单元,触发器的抗功耗攻击水平与电路的安全性能息息相关,为此提出一种抗功耗攻击型触发器。通过引入“预充电-求值-放电”三阶段逻辑,提出了改进型的三阶段动态电流模式逻辑D触发器(improved three-phase dynamic current mode logic-based D flip-flop,TDyCML_FF),避免了因负载电容不均衡引起的电路功耗不恒定等安全问题。同时对三阶段逻辑结构进行了改进,由电路内部节点信号生成放电信号,从而避免通过减缓时钟频率或消除放电信号对其进行攻击,提高了电路的抗功耗攻击性能。通过Hspice仿真实验,并引入归一化能量偏差(NED)和归一化标准偏差(NSD)2个量化参数,将TDyCML_FF感应放大逻辑触发器(SABL_FF)、三阶段双轨预充电逻辑触发器(TDPL_FF)等抗功耗攻击型触发器进行了对比,证明TDyCML_FF具有较高的抗功耗攻击性能。展开更多
基金Suported by Youth Science & Technology Foundation of Ningbo Science & Technology Commission and by Natural Science Foundation of Zhejiang Proyince,China
文摘By using the theory of clipping voltage-switches, two kinds of master/slave nMOS quaternary flip-flops are designed. These flip-flops have the capability of two-input presetting and double-rail complementary outputs. It is shown that these flip-flops are effectively suitable to design nMOS quaternary sequential circuits by designing two examples of hexadecimal up-counter and decimal up-counter.
基金Project(60503027) supported by the National Natural Science Foundation of China
文摘A kind of structure and a design method using transmission voltage-switch theory for pulse-triggered flip-flops were proposed,which are suitable for all kinds of pulse-triggered flip-flops and no extra techniques are needed to eliminate the switching activities of internal nodes.Based on the proposed structure and design technique,two pulsed flip-flops were implemented and simulated.The proposed pulsed flip-flops have simple circuit structures.HSPICE simulation shows that the proposed pulsed D flip-flop outperforms the conventional pulsed D flip-flop by 17.2% in delay and 30.1% in power-delay-product(PDP) and the proposed pulsed JK flip-flop has low power and small PDP compared with pulsed D pulsed flip-flops,confirming that the proposed structure and design technique are simple and practical.
基金Supported by the National Natural Science Foundation of China (No.61274036 and 61106038)Anhui Provincial Natural Science Foundation of China (No.090412034)
文摘In nanoscale technology, transistor aging is one of the most critical problems that impact on the reliability of circuits. Aging sensor is a good online way to detect the circuit aging, which performs during the operating time with no influence of the normal operation of circuits. In this paper, a Dou- ble-edge-triggered Detection Sensor for circuit Aging （DSDA） is proposed, which employs data signal of logic circuits as its clock to control the sampling process. The simulation is done by Hspice using 45 nm technology. The results show that this technique is not case of the detection precision is more than 80% under aging fault effectively with the 8% power cost and 30% sensitive to the process variations. The worst the different process variations. It can detect performance cost.
文摘This research deals with the oscillation mechanism of a flip-flop jet nozzle with a connecting tube, based on the measurements of pressures and velocities in the connecting tube and inside the nozzle. The measurements are carried out varying: 1) the inside diameter d of the connecting tube;2) the length L of the connecting tube and 3) the jet velocity VPN from a primary-nozzle exit. We assume that the jet switches when a time integral reaches a certain value. At first, as the time integral, we introduce the accumulated flow work of pressure, namely, the time integral of mass flux through a connecting tube into the jet-reattaching wall from the opposite jet-un-reattaching wall. Under the assumption, the trace of pressure difference between both the ends of the connecting tube is simply modeled on the basis of measurements, and the flow velocity in the connecting tube is computed as incompressible flow. Second, in order to discuss the physics of the accumulated flow work further, we conduct another experiment in single-port control where the inflow from the control port on the jet-reattaching wall is forcibly controlled and the other control port on the opposite jet-un-reattaching wall is sealed, instead of the experiment in regular jet’s oscillation using the ordinary nozzle with two control ports in connection. As a result, it is found that the accumulated flow work is adequate to determine the dominant jet- oscillation frequency. In the experiment in single-port control, the accumulated flow work of the inflow until the jet’s switching well agrees with that in regular jet’s oscillation using the ordinary nozzle.
基金supported by the ANR project DIPMEM under Grant No.ANR-12-NANO-0010-04
文摘Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory （DRAM） with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops （NVFFs） seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.
基金Supported by the National Natural Science Foundation of Zhejiang Province,China.
文摘According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ternary sequential circuits are implemented by usingarray of universal-logic-modules,U_hs.
基金supported by the National Natural Science Foundation of China(No.61434007)the National Natural Science Foundation of China(No.61704192)
文摘As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of the entire circuit system. Understanding the factors that influence the SET sensitivity of the CDN is crucial to achieving radiation hardening of the CDN and realizing the design of highly reliable ICs. In this paper, the influences of different sequential elements(D-flip-flops and D-latches, the two most commonly used sequential elements in modern synchronous digital systems) on the SET susceptibility of the CDN were quantitatively studied. Electrical simulation and heavy ion experiment results reveal that the CDN-SET-induced incorrect latching is much more likely to occur in DFF and DFF-based designs. This can supply guidelines for the design of IC with high reliability.
基金The Project Supported by National Natural Science Foundation of China
文摘The design of ternary edge-triggered JKL-type flip-flop is proposed.The computersimulation and the test in experimental circuit made up with TTL gate show this flip-flop has theexpected logic functions.
文摘The flow visualization work with the aid of PIV and Piezometer deals with flip-flop flow around diamond-shaped cylinder bundle revised with concavities on both bundle walls. It is disclosed that 1) the concavity constructed on both side-walls of a diamond cylinder induces a substantial change in the flow patterns in the exit jet-stream field and jet- stream dispersion, 2) pressure characteristics are quantitatively measured in a diverging-flow region in diamond cylinder bundles with concavityand in its downstream region, and 3) flip-flop flow occurs in the flow passages and its occurrence condition is obtained.
基金Supported by the National Natural Science Foundation of China （No.60503027） Acknowledgements： The authors are grateful to Prof. Zhao PeiYi of Chapman University, Orange, USA, for beneficial discussions.
文摘Variable supply voltage-clustered voltage scaling （VS-CVS） scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops （LCFFs） are key elements in the CVS scheme. In this paper, a new explicit-pulsed double-edge triggered level converting flip-flop （nEP-DET-LCFF） is proposed, which employs double-edge triggering technique, dynamic structure, explicit pulse generator, conditional discharge technique and proper arrangement of stacked nMOS transistors to efficiently perform latching and level converting functions simultaneously. The proposed nEP-DET-LCFF combines merits of both conventional explicit-LCFFs and implicit-LCFFs. Simulation shows the proposed nEP-DET-LCFF has improvement of 19.2% -46% in delay, and 19.4% - 52.9% in power-delay product （PDP） as compared with the published LCFFs.
文摘A new all optical flip-flop based on a 3-sections nonlinear semiconductor DFB laser structure is proposed and simulated. The operation of the device does not require a holding beam. Electrical current injection into an active layer provides optical gain to the laser mode. The wave-guiding layer consists of a linear grating section centered between 2 detuned nonlinear grating sections. The average refractive index in the nonlinear sections is slightly higher than the refractive index of the middle section. A negative nonlinear refractive index coefficient exists along the nonlinear sections. In the “OFF” state, the DFB structure does not provide enough optical feedback to lase due to the detuned sections. At high light intensity in structure, “ON” state, detuning decreases and the DFB structure allows for a laser mode that sustains the decrease in detuning to exist. The nonlinearity is provided by direct photon absorption at the Urbach tail. Numerical simulations using GPGPU computing show nanoseconds transition times between “OFF” and “ON” states.
文摘A new design for an all optical flip flop is introduced. It is based on a nonlinear Distributed Bragg Reflector (DBR) semiconductor laser structure. The device does not require a holding beam. An optical gain medium confined between 2 Bragg reflectors forms the device. One of the Bragg reflectors is detuned from the other by making its average refractive index slightly higher, and it has a negative nonlinear coefficient that is due to direct absorption at Urbach tail. At low light intensity in the structure, the detuned Bragg reflector does not provide optical feedback to start a laser mode. An optical pulse injected to the structure reduces the detuning of the nonlinear Bragg reflector and a laser mode builds up. The device is reset by detuning the second Bragg reflector optically by an optical pulse that generates electron-hole pairs by direct absorption. A mathematical model of the device is introduced. The model is solved numerically in time domain using a general purpose graphics processing unit (GPGPU) to increase accuracy and to reduce the computation time. The switching dynamics of the device are in nanosecond time scale. The device could be used for all optical data packet switching/routing.
文摘A new all-optical flip-flop based on a nonlinear Distributed feedback (DFB) structure is proposed. The device does not require a holding beam. A nonlinear part of the grating is detuned from the remaining part of the grating and has negative nonlinear coefficient. Optical gain is provided by an injected electrical current into an active layer. In the OFF state, due to the detuned section, no laser light is generated in the device. An injected optical pulse reduces the detuning of the nonlinear section, and the optical feedback provided by the DFB structure generates a laser light in the structure that sustains the change in the detuned section. The device is switched “OFF” by detuning another section of the grating by a Reset pulse. The Reset pulse reduces the refractive index of that section by the generation of electron-hole pairs. The Reset pulse wavelength is adjusted such that the optical gain provided by the active layer at that wavelength is zero. The Reset pulse is prevented from reaching the nonlinear detuned section by introducing an optical absorber in the laser cavity to attenuate the pulse. The device is simulated in time domain using General Purpose Graphics Processing Unit (GPGPU) computing. Set-Reset operations are in nanosecond time scale.
文摘Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.
文摘功耗攻击是一种通过统计电路的功耗信息得到敏感数据信息的攻击手段。作为电路的重要组成单元,触发器的抗功耗攻击水平与电路的安全性能息息相关,为此提出一种抗功耗攻击型触发器。通过引入“预充电-求值-放电”三阶段逻辑,提出了改进型的三阶段动态电流模式逻辑D触发器(improved three-phase dynamic current mode logic-based D flip-flop,TDyCML_FF),避免了因负载电容不均衡引起的电路功耗不恒定等安全问题。同时对三阶段逻辑结构进行了改进,由电路内部节点信号生成放电信号,从而避免通过减缓时钟频率或消除放电信号对其进行攻击,提高了电路的抗功耗攻击性能。通过Hspice仿真实验,并引入归一化能量偏差(NED)和归一化标准偏差(NSD)2个量化参数,将TDyCML_FF感应放大逻辑触发器(SABL_FF)、三阶段双轨预充电逻辑触发器(TDPL_FF)等抗功耗攻击型触发器进行了对比,证明TDyCML_FF具有较高的抗功耗攻击性能。
