This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate t...This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate the impact of well contact distance on the FinFET process.The experimental results show that the SET pulse width has a bimodal symmetric distribution,which is different from that of a bulk planar CMOS device.To investigate the detailed mechanism of the phenomenon,a high-precision FinFET TCAD model was established,in which both Id-Vd and Id-Vg errors were less than 10%compared to the SPICE model provided by the commercial process.TCAD simulation under heavy ion injection showed the mechanism of the abnormal phenomenon,where the well contact plays a major role in charge collection at the near-well contact distance,while the source plays a major role at the far distance.This phenomenon is completely different from that of planar CMOS devices.This indicates that the SET mechanism becomes more complicated during the FinFET process.Therefore,more effective SET hardening methods should be investigated for FinFET.展开更多
A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabric...A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabrication processes are fully compatible with conventional CMOS process,including salicide technology.The CMOS device,inverter,and CMOS ring oscillator of this structure with normal poly silicon and W/TiN gate electrode are fabricated respectively.Driving current and sub threshold characteristics of CMOS FinFET on Si substrate with actual gate length of 110nm are studied.The inverter operates correctly and minimum per stage delay of 201 stage ring oscillator is 146ps at V d=3V.The result indicates the device is a promising candidate for the application of future VLSI circuit.展开更多
An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well c...An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well controlled by reducing fin height.Good performance can be achieved with thin height,so fin height is considered as a key parameter in device design.Simulation results show that FINFETs present performance superior to conventional single gate devices.展开更多
基金supported by Natural Science Foundation of China(Nos.62174180 and 62304258)National Key R&D Program of China(No.2023YFA1609000)。
文摘This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate the impact of well contact distance on the FinFET process.The experimental results show that the SET pulse width has a bimodal symmetric distribution,which is different from that of a bulk planar CMOS device.To investigate the detailed mechanism of the phenomenon,a high-precision FinFET TCAD model was established,in which both Id-Vd and Id-Vg errors were less than 10%compared to the SPICE model provided by the commercial process.TCAD simulation under heavy ion injection showed the mechanism of the abnormal phenomenon,where the well contact plays a major role in charge collection at the near-well contact distance,while the source plays a major role at the far distance.This phenomenon is completely different from that of planar CMOS devices.This indicates that the SET mechanism becomes more complicated during the FinFET process.Therefore,more effective SET hardening methods should be investigated for FinFET.
文摘A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabrication processes are fully compatible with conventional CMOS process,including salicide technology.The CMOS device,inverter,and CMOS ring oscillator of this structure with normal poly silicon and W/TiN gate electrode are fabricated respectively.Driving current and sub threshold characteristics of CMOS FinFET on Si substrate with actual gate length of 110nm are studied.The inverter operates correctly and minimum per stage delay of 201 stage ring oscillator is 146ps at V d=3V.The result indicates the device is a promising candidate for the application of future VLSI circuit.
文摘An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well controlled by reducing fin height.Good performance can be achieved with thin height,so fin height is considered as a key parameter in device design.Simulation results show that FINFETs present performance superior to conventional single gate devices.
