Since the lower power requirement of code division multiple access(CDMA) than that of other multiple access, the CDMA technology is suitable to be used in low earth orbit(LEO) satellite communication system whose spac...Since the lower power requirement of code division multiple access(CDMA) than that of other multiple access, the CDMA technology is suitable to be used in low earth orbit(LEO) satellite communication system whose space power is limited due to the small size of satellite. The pilot channel of CDMA technology is very important for earth mobile station(EMS) in LEO system to recover carrier and code, but the power requirement of pilot channel is very higher than that of other channels. In this paper, a power reduction method for pilot channel is proposed. By the new method, the power of pilot channel transmitted from LEO satellite is reduced to a lower level. For improving the signal to noise ratio(SNR) of pilot channel with lower power, coherent integration is employed in EMS at the pre-processing stage. Considering the high dynamic situation of LEO satellite, the long period of time for integration will deteriorate the receiving performance of EMS, therefore, a dynamic compensation module is added to carrier tracking loop against the high dynamic. Meanwhile, the transfer function of the new tracking loop and the condition for steadystate zero error are deduced. Numerical examples are provided to demonstrate effectiveness of the proposed approach.展开更多
The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically ab...The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically about 30% to 70% of the total dynamic (switching) power consumption. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. In this work, a new methodology is applied for gating the Flip flop by which the power will be reduced. The clock gating is employed to the pipelining stage flip flop which is active only during valid data are arrived. The methodology used in project named Selective Look-Ahead Clock Gating computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. Similarly to data-driven gating, it is capable of stopping the majority of redundant clock pulses. In this work, the circuit implementation of the various blocks of data driven clock gating is done and the results are observed. The proposed work is used for pipelining stage in microprocessor and DSP architectures. The proposed method is simulated using the quartus for cyclone 3 kit.展开更多
基金supported by the National High Technology Research and Development Program of China (863 Program) (No.2012AA01A502)the National Natural Science Foundation of China (No.61179006)the Science and Technology Support Program of Sichuan Province (No.2014GZX0004)
文摘Since the lower power requirement of code division multiple access(CDMA) than that of other multiple access, the CDMA technology is suitable to be used in low earth orbit(LEO) satellite communication system whose space power is limited due to the small size of satellite. The pilot channel of CDMA technology is very important for earth mobile station(EMS) in LEO system to recover carrier and code, but the power requirement of pilot channel is very higher than that of other channels. In this paper, a power reduction method for pilot channel is proposed. By the new method, the power of pilot channel transmitted from LEO satellite is reduced to a lower level. For improving the signal to noise ratio(SNR) of pilot channel with lower power, coherent integration is employed in EMS at the pre-processing stage. Considering the high dynamic situation of LEO satellite, the long period of time for integration will deteriorate the receiving performance of EMS, therefore, a dynamic compensation module is added to carrier tracking loop against the high dynamic. Meanwhile, the transfer function of the new tracking loop and the condition for steadystate zero error are deduced. Numerical examples are provided to demonstrate effectiveness of the proposed approach.
文摘The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically about 30% to 70% of the total dynamic (switching) power consumption. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. In this work, a new methodology is applied for gating the Flip flop by which the power will be reduced. The clock gating is employed to the pipelining stage flip flop which is active only during valid data are arrived. The methodology used in project named Selective Look-Ahead Clock Gating computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. Similarly to data-driven gating, it is capable of stopping the majority of redundant clock pulses. In this work, the circuit implementation of the various blocks of data driven clock gating is done and the results are observed. The proposed work is used for pipelining stage in microprocessor and DSP architectures. The proposed method is simulated using the quartus for cyclone 3 kit.
