This article introduces a novel 20 V radiation-hardened high-voltage metal-oxide-semiconductor field-effect transistor(MOSFET)driver with an optimized input circuit and a drain-surrounding-source(DSS)structure.The inp...This article introduces a novel 20 V radiation-hardened high-voltage metal-oxide-semiconductor field-effect transistor(MOSFET)driver with an optimized input circuit and a drain-surrounding-source(DSS)structure.The input circuit of a conventional inverter consists of a thick-gate-oxide n-type MOSFET(NMOS).These conventional drivers can tolerate a total ionizing dose(TID)of up to 100 krad(Si).In contrast,the proposed comparator input circuit uses both a thick-gate-oxide p-type MOSFET(PMOS)and thin-gate-oxide NMOS to offer a high input voltage and higher TID tolerance.Because the thick-gate-oxide PMOS and thin-gate-oxide NMOS collectively provide better TID tolerance than the thick-gate-oxide NMOS,the circuit exhibits enhanced TID tolerance of>300 krad(Si).Simulations and experimental date indicate that the DSS structure reduces the probability of unwanted parasitic bipolar junction transistor activation,yielding a better single-event effect tolerance of over 81.8 MeVcm^(2)mg^(-1).The innovative strategy proposed in this study involves circuit and layout design optimization,and does not require any specialized process flow.Hence,the proposed circuit can be manufactured using common commercial 0.35μm BCD processes.展开更多
基金supported by the National Natural Science Foundation of China(U2241221).
文摘This article introduces a novel 20 V radiation-hardened high-voltage metal-oxide-semiconductor field-effect transistor(MOSFET)driver with an optimized input circuit and a drain-surrounding-source(DSS)structure.The input circuit of a conventional inverter consists of a thick-gate-oxide n-type MOSFET(NMOS).These conventional drivers can tolerate a total ionizing dose(TID)of up to 100 krad(Si).In contrast,the proposed comparator input circuit uses both a thick-gate-oxide p-type MOSFET(PMOS)and thin-gate-oxide NMOS to offer a high input voltage and higher TID tolerance.Because the thick-gate-oxide PMOS and thin-gate-oxide NMOS collectively provide better TID tolerance than the thick-gate-oxide NMOS,the circuit exhibits enhanced TID tolerance of>300 krad(Si).Simulations and experimental date indicate that the DSS structure reduces the probability of unwanted parasitic bipolar junction transistor activation,yielding a better single-event effect tolerance of over 81.8 MeVcm^(2)mg^(-1).The innovative strategy proposed in this study involves circuit and layout design optimization,and does not require any specialized process flow.Hence,the proposed circuit can be manufactured using common commercial 0.35μm BCD processes.
