With the development of VLSI technology, testing design method has been one indispensable fact of the research of VLSI design methodology. Technology of testing design can observably reduce the cost of the chip and he...With the development of VLSI technology, testing design method has been one indispensable fact of the research of VLSI design methodology. Technology of testing design can observably reduce the cost of the chip and help win in time- to-market. Conventional methods of design for test improve the testing performance of the system by modifing the gate-level architecture generally. Re-search in high-level test synthesis has been emphasized on fitting for the trend of high-level VLSI design. In this paper, based on the analysis of different types of testing design methods, a novel compound strategy of design for test in VLSI system is proposed.展开更多
As Moore’s Law approaches its limits,3-D integrated circuits(ICs)have emerged as promising alternatives to conventional scaling methodologies.However,the benefits of 3-D integration in terms of lower power consumptio...As Moore’s Law approaches its limits,3-D integrated circuits(ICs)have emerged as promising alternatives to conventional scaling methodologies.However,the benefits of 3-D integration in terms of lower power consumption,higher performance,and reduced area are accompanied by testing challenges.The unique vertical stacking of components in 3-D ICs introduces concerns related to the robustness of bonding surfaces.Moreover,immature manufacturing processes during 3-D fabrication can lead to high defect rates in different tiers.Therefore,there is a need for design-for-test solutions to ensure the reliability and performance of 3-D-integrated architectures.In this paper,we provide a comprehensive survey of existing testing strategies for 3-D ICs.We describe recent advances,including research efforts and industry practice,that address concerns related to bonding defects,elevated power supply noise,fault diagnosis,and fault localization specific to the unique characteristics of 3-D ICs.展开更多
Scan-based design for test （DFT） is a powerful and the most popular testing technique. However, while scan-based DFT improves test efficiency, it also leaves a side channel to the privacy information stored in the c...Scan-based design for test （DFT） is a powerful and the most popular testing technique. However, while scan-based DFT improves test efficiency, it also leaves a side channel to the privacy information stored in the chip. This paper investigates the side channel and proposes a simple but powerful scan-based attack that can reveal the key and/or state stored in the chips that implement the state-of-the-art stream ciphers with less than 85 scan-out vectors.展开更多
文摘With the development of VLSI technology, testing design method has been one indispensable fact of the research of VLSI design methodology. Technology of testing design can observably reduce the cost of the chip and help win in time- to-market. Conventional methods of design for test improve the testing performance of the system by modifing the gate-level architecture generally. Re-search in high-level test synthesis has been emphasized on fitting for the trend of high-level VLSI design. In this paper, based on the analysis of different types of testing design methods, a novel compound strategy of design for test in VLSI system is proposed.
基金supported in part by the National Science Foundation under Grant CCF-1908045 and Grant CCF-2309822in part by the Semiconductor Research Corporation(SRC)under Contract 2470+3 种基金in part by Intel Corporationin part by the DARPA ERI 3DSOC program under Award HR001118C0096in part by CHIMES,one of the seven centers in JUMP 2.0in part by DARPA through SRC Program.
文摘As Moore’s Law approaches its limits,3-D integrated circuits(ICs)have emerged as promising alternatives to conventional scaling methodologies.However,the benefits of 3-D integration in terms of lower power consumption,higher performance,and reduced area are accompanied by testing challenges.The unique vertical stacking of components in 3-D ICs introduces concerns related to the robustness of bonding surfaces.Moreover,immature manufacturing processes during 3-D fabrication can lead to high defect rates in different tiers.Therefore,there is a need for design-for-test solutions to ensure the reliability and performance of 3-D-integrated architectures.In this paper,we provide a comprehensive survey of existing testing strategies for 3-D ICs.We describe recent advances,including research efforts and industry practice,that address concerns related to bonding defects,elevated power supply noise,fault diagnosis,and fault localization specific to the unique characteristics of 3-D ICs.
基金partially supported by the National High Technology Research and Development 863 Program of China under Grant No.2013AA013202the Key Programs for Science and Technology Development of Chongqing of China under Grant No.cstc2012ggC40005+1 种基金the National Natural Science Foundation of China under Grant No.61173014the National Science Foundation of USA under Grant No.CNS-1015802
文摘Scan-based design for test （DFT） is a powerful and the most popular testing technique. However, while scan-based DFT improves test efficiency, it also leaves a side channel to the privacy information stored in the chip. This paper investigates the side channel and proposes a simple but powerful scan-based attack that can reveal the key and/or state stored in the chips that implement the state-of-the-art stream ciphers with less than 85 scan-out vectors.
