An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating mo...An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.展开更多
The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is o...The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus （BP） by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10 V/nm to 0.83 V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronies, thermoelectric power generation and thermal imaging.展开更多
在TFT-LCD驱动的关键设计技术中,抖动算法FRC(frame rate control)是一种重要的技术。它能够用6 bit source的输出来达到8 bit full color(16.7 M colors)的显示效果,这样可以降低数据传输率以降低功耗,同时可以节省源驱动(Source Drive...在TFT-LCD驱动的关键设计技术中,抖动算法FRC(frame rate control)是一种重要的技术。它能够用6 bit source的输出来达到8 bit full color(16.7 M colors)的显示效果,这样可以降低数据传输率以降低功耗,同时可以节省源驱动(Source Driver,SD)芯片的面积。通过分析和实践,提出了针对用于平板电脑的Dual-Gate TFT-LCD屏和翻转方式,需要采用优化的FRC算法提高显示效果。在应用于平板电脑的dual-gate TFT-LCD屏的FRC方案中,分析了传统方案产生周期性竖线的原因,然后提出了改进方案,消除了竖线,提高了显示质量。最后,总结了FRC算法具体需要考虑的因素。展开更多
An analytical drain current model on the basis of the surface potential is proposed for indium-gallium zinc oxide(InGaZnO)thin-film transistors(TFTs)with an independent dual-gate(IDG)structure.For a unified expression...An analytical drain current model on the basis of the surface potential is proposed for indium-gallium zinc oxide(InGaZnO)thin-film transistors(TFTs)with an independent dual-gate(IDG)structure.For a unified expression of carriers’distribution for the sub-threshold region and the conduction region,the concept of equivalent flat-band voltage and the Lambert W function are introduced to solve the Poisson equation,and to derive the potential distribution of the active layer.In addition,the regional integration approach is used to develop a compact analytical current-voltage model.Although only two fitting parameters are required,a good agreement is obtained between the calculated results by the proposed model and the simulation results by TCAD.The proposed current-voltage model is then implemented by using Verilog-A for SPICE simulations of a dual-gate InGaZnO TFT integrated inverter circuit.展开更多
Semiconductive two dimensional(2D)materials have attracted significant research attention due to their rich band structures and promising potential for next-generation electrical devices.In this work,we investigate th...Semiconductive two dimensional(2D)materials have attracted significant research attention due to their rich band structures and promising potential for next-generation electrical devices.In this work,we investigate the MoS2 field-effect transistors(FETs)with a dual-gated(DG)architecture,which consists of symmetrical thickness for back gate(BG)and top gate(TG)dielectric.The thickness-dependent charge transport in our DG-MoS2 device is revealed by a four-terminal electrical measurement which excludes the contact influence,and the TCAD simulation is also applied to explain the experimental data.Our results indicate that the impact of quantum confinement effect plays an important role in the charge transport in the MoS2 channel,as it confines charge carriers in the center of the channel,which reduces the scattering and boosts the mobility compared to the single gating case.Furthermore,temperature-dependent transfer curves reveal that multi-layer MoS2 DG-FET is in the phonon-limited transport regime,while single layer MoS2 shows typical Coulomb impurity limited regime.展开更多
A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and...A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.展开更多
Organic field-effect transistors (OFETs), with their potential for low-cost manufacturing and compatibility with flexible substrates,have emerged as an indispensable element in next-generation electronics. However, th...Organic field-effect transistors (OFETs), with their potential for low-cost manufacturing and compatibility with flexible substrates,have emerged as an indispensable element in next-generation electronics. However, the existing OFETs are significantlyhindered by their lack of reconfigurability and multifunctionality for application in complex electronic systems. To addressthese limitations, we propose a novel design strategy to develop a dual-gate organic field-effect transistor (DG-OFET), primarilyfeaturing a synergistic combination of interface charge trapping and the nonvolatile nature of ferroelectric polarization, whichrealizes the multifunctional integration within a single platform. Specifically, the DG-OFET can be utilized as synaptic devicesthat can successfully perform both short-term and long-term synaptic plasticity by manipulating the input gate of artificial pulsevoltages, depending on the switching mechanism between bottom-gate controlled electrostatic doping and top-gate inducedferroelectric polarization. Besides, the presynaptic spike applied to a specific gate electrode can trigger the excitatory andinhibitory postsynaptic current response. The potentiation and depression of synaptic weight are mimicked by consecutivepositive and negative spikes, respectively. The dual-gate coupling strategy further expands its functionality towards simulatingthe operation of logic gates. By modulating the combination of dual-gate input signals, the channel conductivity can analogouslyperform a family of elementary Boolean logic operations, including AND, OR, NAND, NOR, XOR, and XNOR. Theseresults highlight the electronic reconfigurability of DG-OFET and tremendous potential for applications in energy-efficientneuromorphic computing networks and organic circuits, thus providing a versatile strategy for the development of advancedand efficient multifunctional integration.展开更多
Two-dimensional(2D)transition metal dichalcogenides(TMDs)such as molybdenum disulfide(M0S2)have been intensively investigated because of their exclusive physical properties for advaneed electronics and optoelectronics...Two-dimensional(2D)transition metal dichalcogenides(TMDs)such as molybdenum disulfide(M0S2)have been intensively investigated because of their exclusive physical properties for advaneed electronics and optoelectronics.In the present work,we study the M0S2 transistor based on a novel tri-gate device architecture,with dual-gate(Dual-G)in the channel and the buried side-gate(Side-G)for the source/drain regi ons.All gates can be in depe ndently con trolled without in terfere nee.For a MoS2 sheet with a thick ness of 3.6 nm,the Schottky barrier(SB)and non-overlapped channel region can be effectively tuned by electrostatically doping the source/drain regions with Side-G.Thus,the extri nsic resista nee can be effectively lowered,and a boost of the ON-state cur re nt can be achieved.Mean while,the cha nn el c ontrol remai ns efficient under the Dual-G mode,with an ON-OFF current ratio of 3 x 107 and subthreshold swing of 83 mV/decade.The corresponding band diagram is also discussed to illustrate the device operati on mechanism.This no vel device structure ope ns up a new way toward fabricati on of high-performance devices based on 2D-TMDs.展开更多
Accounting for the deep Gaussian and tail exponential distribution of the density of states, a physical approximation for potentials of amorphous silicon thin-film transistors using a symmetric dual gate （sDG a-Si：H...Accounting for the deep Gaussian and tail exponential distribution of the density of states, a physical approximation for potentials of amorphous silicon thin-film transistors using a symmetric dual gate （sDG a-Si：H TFT） has been presented. The proposed scheme provides a complete solution of the potentials at the surface and center of the layer without solving any transcendental equations. A channel current model incorporating features of gate voltage-dependent mobility and coupling factor is derived. We show the parameters required for accurately describing the current-voltage （l-V） characteristics of DG a-Si：H TFT and just how sensitively these parameters affect TFT current. Particularly, the parameters＇ dependence on the I-V characteristics with respect to the density of deep state and channel thickness has been investigated in detail. The resulting scheme and model are successively verified through comparison with numerical simulations as well as the available experimental data.展开更多
基金Supported by the National Key Research and Development Program of China under Grant No 2017YFA0204600the National Natural Science Foundation of China under Grant No 61404002the Science and Technology Project of Hunan Province under Grant No 2015JC3041
文摘An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.
基金Supported by the National Basic Research Program of China under Grant Nos 2013CB921900 and 2014CB920900the National Natural Science Foundation of China under Grant No 11374021)(S.Yan,Z.Xie,J.-H,Chen)+1 种基金support from the Elemental Strategy Initiative conducted by the MEXT,Japana Grant-in-Aid for Scientific Research on Innovative Areas"Science of Atomic Layers"from JSPS
文摘The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus （BP） by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10 V/nm to 0.83 V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronies, thermoelectric power generation and thermal imaging.
文摘在TFT-LCD驱动的关键设计技术中,抖动算法FRC(frame rate control)是一种重要的技术。它能够用6 bit source的输出来达到8 bit full color(16.7 M colors)的显示效果,这样可以降低数据传输率以降低功耗,同时可以节省源驱动(Source Driver,SD)芯片的面积。通过分析和实践,提出了针对用于平板电脑的Dual-Gate TFT-LCD屏和翻转方式,需要采用优化的FRC算法提高显示效果。在应用于平板电脑的dual-gate TFT-LCD屏的FRC方案中,分析了传统方案产生周期性竖线的原因,然后提出了改进方案,消除了竖线,提高了显示质量。最后,总结了FRC算法具体需要考虑的因素。
基金Project supported by the National Key Research and Development Program of China(Grant No.2017YFA0204600)the Fundamental Research Funds for the Central Universities of Central South University,China(Grant No.2019zzts424)。
文摘An analytical drain current model on the basis of the surface potential is proposed for indium-gallium zinc oxide(InGaZnO)thin-film transistors(TFTs)with an independent dual-gate(IDG)structure.For a unified expression of carriers’distribution for the sub-threshold region and the conduction region,the concept of equivalent flat-band voltage and the Lambert W function are introduced to solve the Poisson equation,and to derive the potential distribution of the active layer.In addition,the regional integration approach is used to develop a compact analytical current-voltage model.Although only two fitting parameters are required,a good agreement is obtained between the calculated results by the proposed model and the simulation results by TCAD.The proposed current-voltage model is then implemented by using Verilog-A for SPICE simulations of a dual-gate InGaZnO TFT integrated inverter circuit.
基金supported by the National Key Research and Development Program of China(2016YFA0203900,2018YFA0306101)the National Natural Science Foundation of China(Grant No.91964202)Shanghai Municipal Science and Technology Commission(18JC1410300)。
文摘Semiconductive two dimensional(2D)materials have attracted significant research attention due to their rich band structures and promising potential for next-generation electrical devices.In this work,we investigate the MoS2 field-effect transistors(FETs)with a dual-gated(DG)architecture,which consists of symmetrical thickness for back gate(BG)and top gate(TG)dielectric.The thickness-dependent charge transport in our DG-MoS2 device is revealed by a four-terminal electrical measurement which excludes the contact influence,and the TCAD simulation is also applied to explain the experimental data.Our results indicate that the impact of quantum confinement effect plays an important role in the charge transport in the MoS2 channel,as it confines charge carriers in the center of the channel,which reduces the scattering and boosts the mobility compared to the single gating case.Furthermore,temperature-dependent transfer curves reveal that multi-layer MoS2 DG-FET is in the phonon-limited transport regime,while single layer MoS2 shows typical Coulomb impurity limited regime.
基金Project supported by the National Natural Science Foundation of China (Grant No. 61176069)the National Key Laboratory of Analog Integrated Circuit,China (Grant No. 9140C090304110C0905)the Innovation Foundation of the State Key Laboratory of Electronic Thin Films and Integrated Devices,China (Grant No. CXJJ201004)
文摘A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.
基金supported by the Ministry of Science and Technology of the People's Republic of China(2022YFB3603804)Natural Science Foundation of Shanghai Municipality(22ZR1407800).
文摘Organic field-effect transistors (OFETs), with their potential for low-cost manufacturing and compatibility with flexible substrates,have emerged as an indispensable element in next-generation electronics. However, the existing OFETs are significantlyhindered by their lack of reconfigurability and multifunctionality for application in complex electronic systems. To addressthese limitations, we propose a novel design strategy to develop a dual-gate organic field-effect transistor (DG-OFET), primarilyfeaturing a synergistic combination of interface charge trapping and the nonvolatile nature of ferroelectric polarization, whichrealizes the multifunctional integration within a single platform. Specifically, the DG-OFET can be utilized as synaptic devicesthat can successfully perform both short-term and long-term synaptic plasticity by manipulating the input gate of artificial pulsevoltages, depending on the switching mechanism between bottom-gate controlled electrostatic doping and top-gate inducedferroelectric polarization. Besides, the presynaptic spike applied to a specific gate electrode can trigger the excitatory andinhibitory postsynaptic current response. The potentiation and depression of synaptic weight are mimicked by consecutivepositive and negative spikes, respectively. The dual-gate coupling strategy further expands its functionality towards simulatingthe operation of logic gates. By modulating the combination of dual-gate input signals, the channel conductivity can analogouslyperform a family of elementary Boolean logic operations, including AND, OR, NAND, NOR, XOR, and XNOR. Theseresults highlight the electronic reconfigurability of DG-OFET and tremendous potential for applications in energy-efficientneuromorphic computing networks and organic circuits, thus providing a versatile strategy for the development of advancedand efficient multifunctional integration.
基金This work was supported by the National Key Research and Development Program of China(Nos.2016YFA0203900 and 2018YFA0306101)Shanghai Municipal Science and Technology Commission(No.18JC1410300)Natural Science Foundation of China(No.61874154).
文摘Two-dimensional(2D)transition metal dichalcogenides(TMDs)such as molybdenum disulfide(M0S2)have been intensively investigated because of their exclusive physical properties for advaneed electronics and optoelectronics.In the present work,we study the M0S2 transistor based on a novel tri-gate device architecture,with dual-gate(Dual-G)in the channel and the buried side-gate(Side-G)for the source/drain regi ons.All gates can be in depe ndently con trolled without in terfere nee.For a MoS2 sheet with a thick ness of 3.6 nm,the Schottky barrier(SB)and non-overlapped channel region can be effectively tuned by electrostatically doping the source/drain regions with Side-G.Thus,the extri nsic resista nee can be effectively lowered,and a boost of the ON-state cur re nt can be achieved.Mean while,the cha nn el c ontrol remai ns efficient under the Dual-G mode,with an ON-OFF current ratio of 3 x 107 and subthreshold swing of 83 mV/decade.The corresponding band diagram is also discussed to illustrate the device operati on mechanism.This no vel device structure ope ns up a new way toward fabricati on of high-performance devices based on 2D-TMDs.
基金supported by the National Natural Science Foundation of China(No.61274085)the Cadence Design System,Inc
文摘Accounting for the deep Gaussian and tail exponential distribution of the density of states, a physical approximation for potentials of amorphous silicon thin-film transistors using a symmetric dual gate （sDG a-Si：H TFT） has been presented. The proposed scheme provides a complete solution of the potentials at the surface and center of the layer without solving any transcendental equations. A channel current model incorporating features of gate voltage-dependent mobility and coupling factor is derived. We show the parameters required for accurately describing the current-voltage （l-V） characteristics of DG a-Si：H TFT and just how sensitively these parameters affect TFT current. Particularly, the parameters＇ dependence on the I-V characteristics with respect to the density of deep state and channel thickness has been investigated in detail. The resulting scheme and model are successively verified through comparison with numerical simulations as well as the available experimental data.
