随着工艺制程的不断微缩,动态随机存储器(dynamic random access memory,DRAM)的集成度持续提高,单颗芯片上存储单元的数目呈指数增长,随之带来的是芯片发热严重和泄漏电流增大等问题,为了实时监测内部温度并控制相应的刷新操作,DRAM需...随着工艺制程的不断微缩,动态随机存储器(dynamic random access memory,DRAM)的集成度持续提高,单颗芯片上存储单元的数目呈指数增长,随之带来的是芯片发热严重和泄漏电流增大等问题,为了实时监测内部温度并控制相应的刷新操作,DRAM需要在内部集成温度传感器。文章从DRAM的基本结构、工作原理和实际工作中对内置温度传感器的需求出发,研究不同读出架构的集成式温度传感器的优缺点,考虑到感温精度、感温范围、功耗和成本等因素以及DRAM产品规格说明书中对内置温度传感器的要求,设计出一款基于时域读出架构的免校准低功耗温度传感器。采用19 nm的互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)工艺进行仿真验证,结果表明,免校准的前提下,该温度传感器在0~110℃的感温范围内具有3℃的仿真精度,版图面积为0.189 mm^(2),平均功耗为340.31μW,感温时间为550μs。文章设计的温度传感器满足DRAM对于内置温度传感器的要求,且大大降低了DRAM的生产成本。展开更多
Capacitor-less 2T0C dynamic random-access memory(DRAM)employing oxide semiconductors(OSs)as a channel has great potential in the development of highly scaled three dimensional(3D)-structured devices.However,the use of...Capacitor-less 2T0C dynamic random-access memory(DRAM)employing oxide semiconductors(OSs)as a channel has great potential in the development of highly scaled three dimensional(3D)-structured devices.However,the use of OS and such device structures presents certain challenges,including the trade-off relationship between the field-effect mobility and stability of OSs.Conventional 4-line-based operation of the 2T0C enlarges the entire cell volume and complicates the peripheral circuit.Herein,we proposed an IGO(In-Ga-O)channel 2-line-based 2T0C cell design and operating sequences comparable to those of the conventional Si-channel 1 T1C DRAM.IGO was adopted to achieve high thermal stability above 800℃,and the process conditions were optimized to simultaneously obtain a high μFE of 90.7 cm^(2)·V^(-)1·s^(-1),positive Vth of 0.34 V,superior reliability,and uniformity.The proposed 2-line-based 2T0C DRAM cell successfully exhibited multi-bit operation,with the stored voltage varying from 0 V to 1 V at 0.1 V intervals.Furthermore,for stored voltage intervals of 0.1 V and 0.5 V,the refresh time was 10 s and 1000 s in multi-bit operation;these values were more than 150 and 15000 times longer than those of the conventional Si channel 1T1C DRAM,respectively.A monolithic stacked 2-line-based 2T0C DRAM was fabricated,and a multi-bit operation was confirmed.展开更多
DRAM作为计算机存储系统的核心组件,在HPC、云计算、AI等领域至关重要。然而,传统1T1C DRAM受电容缩放瓶颈、刷新功耗及制造复杂度等问题限制,难以满足先进制程需求。2T0C DRAM采用双晶体管架构,利用浮体效应、栅极耦合等机制存储电荷,...DRAM作为计算机存储系统的核心组件,在HPC、云计算、AI等领域至关重要。然而,传统1T1C DRAM受电容缩放瓶颈、刷新功耗及制造复杂度等问题限制,难以满足先进制程需求。2T0C DRAM采用双晶体管架构,利用浮体效应、栅极耦合等机制存储电荷,实现高密度、低功耗及工艺兼容性提升。本研究分析2T0C DRAM的技术原理、结构设计及其相较于1T1C DRAM的优势,探讨数据保持、读写干扰、工艺变异等挑战,并综述器件优化、电路创新及先进制造工艺的应对策略。此外,结合CIM、3D集成等趋势,探讨其在HPC、嵌入式及新型存储中的应用价值。当前,三星、美光等厂商已展开2T0C DRAM研发,预计未来逐步进入量产。随着半导体工艺演进,2T0C DRAM有望成为下一代高密度、低功耗存储技术。然而,量子效应、工艺适配及产业链完善仍是关键挑战。未来研究将聚焦器件微缩、存算一体及异质集成,推动2T0C DRAM发展与产业化进程。As a core component of computer memory systems, DRAM plays a critical role in HPC, cloud computing, and AI. However, traditional 1T1C DRAM faces challenges such as capacitor scaling limitations, high refresh power consumption, and increasing fabrication complexity, restricting its scalability in advanced process nodes. To address these issues, 2T0C DRAM adopts a two-transistor architecture, utilizing floating-body effects and gate coupling mechanisms to store charge, thereby enhancing storage density, reducing power consumption, and improving process compatibility. This study analyzes the technical principles and structural design of 2T0C DRAM, highlighting its advantages over 1T1C DRAM while addressing challenges such as data retention, read/write disturbances, and process variations. Various optimization strategies, including device engineering, circuit design innovations, and advanced fabrication techniques, are also reviewed. Furthermore, considering emerging trends like CIM and 3D integration, we explore the potential applications of 2T0C DRAM in HPC, embedded systems, and next-generation memory technologies. Currently, leading memory manufacturers such as Samsung and Micron have initiated research on 2T0C DRAM, with commercialization expected in the near future. With the continuous advancement of semiconductor technology, 2T0C DRAM is poised to become a key candidate for next-generation high-density, low-power memory solutions. However, challenges such as quantum effects, process adaptation, and supply chain maturity remain critical. Future research will focus on device scaling, in-memory computing, and heterogeneous integration to accelerate the development and industrialization of 2T0C DRAM.展开更多
p53凋亡刺激蛋白2(apoptosis stimulating protein 2 of p53,ASPP2)能特异性地与p53蛋白结合并增强其促凋亡的功能,进而发挥抗肿瘤作用.本室前期研究发现,ASPP2可以通过p53-DRAM-自噬途径诱导细胞凋亡.在本研究中,利用ASPP2腺病毒感染He...p53凋亡刺激蛋白2(apoptosis stimulating protein 2 of p53,ASPP2)能特异性地与p53蛋白结合并增强其促凋亡的功能,进而发挥抗肿瘤作用.本室前期研究发现,ASPP2可以通过p53-DRAM-自噬途径诱导细胞凋亡.在本研究中,利用ASPP2腺病毒感染Hep3B细胞(p53缺陷型肝癌细胞系)并用甲基磺酸(MMS)处理后;Calcein AM/PI和M30染色检测细胞凋亡;GFP-LC3质粒转染细胞后检测自噬;荧光定量PCR和免疫印迹检测自噬基因表达.结果表明,ASPP2在p53缺陷的Hep3B细胞内可诱导发生凋亡;在MMS存在和缺失条件下,Adr-ASPP2均引起自噬体水平升高及自噬基因的表达增加,且MMS协同Adr-ASPP2能使自噬水平增加;进一步用VPS34 siRNA和DRAM siRNA抑制自噬发现,细胞凋亡水平下降,说明由Adr-ASPP2诱发经损伤相关自噬调节蛋白(DRAM)介导的自噬参与了肝癌细胞系凋亡的发生.综上结果表明,ASPP2可以通过非p53依赖的DRAM介导自噬,并促进肝癌细胞凋亡.该研究可为肝癌的基因治疗提供新的思路.展开更多
文摘随着工艺制程的不断微缩,动态随机存储器(dynamic random access memory,DRAM)的集成度持续提高,单颗芯片上存储单元的数目呈指数增长,随之带来的是芯片发热严重和泄漏电流增大等问题,为了实时监测内部温度并控制相应的刷新操作,DRAM需要在内部集成温度传感器。文章从DRAM的基本结构、工作原理和实际工作中对内置温度传感器的需求出发,研究不同读出架构的集成式温度传感器的优缺点,考虑到感温精度、感温范围、功耗和成本等因素以及DRAM产品规格说明书中对内置温度传感器的要求,设计出一款基于时域读出架构的免校准低功耗温度传感器。采用19 nm的互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)工艺进行仿真验证,结果表明,免校准的前提下,该温度传感器在0~110℃的感温范围内具有3℃的仿真精度,版图面积为0.189 mm^(2),平均功耗为340.31μW,感温时间为550μs。文章设计的温度传感器满足DRAM对于内置温度传感器的要求,且大大降低了DRAM的生产成本。
基金supported by the Technology Innovation Program(Grant Nos.20017382 and 20023023)funded by the Ministry of Trade,Industry&Energy(MOTIE,Republic of Korea)supported by a National Research Foundation of Korea(NRF)grant funded by the Korean Government(MSIT)(Grant No.RS-2023-00260527).
文摘Capacitor-less 2T0C dynamic random-access memory(DRAM)employing oxide semiconductors(OSs)as a channel has great potential in the development of highly scaled three dimensional(3D)-structured devices.However,the use of OS and such device structures presents certain challenges,including the trade-off relationship between the field-effect mobility and stability of OSs.Conventional 4-line-based operation of the 2T0C enlarges the entire cell volume and complicates the peripheral circuit.Herein,we proposed an IGO(In-Ga-O)channel 2-line-based 2T0C cell design and operating sequences comparable to those of the conventional Si-channel 1 T1C DRAM.IGO was adopted to achieve high thermal stability above 800℃,and the process conditions were optimized to simultaneously obtain a high μFE of 90.7 cm^(2)·V^(-)1·s^(-1),positive Vth of 0.34 V,superior reliability,and uniformity.The proposed 2-line-based 2T0C DRAM cell successfully exhibited multi-bit operation,with the stored voltage varying from 0 V to 1 V at 0.1 V intervals.Furthermore,for stored voltage intervals of 0.1 V and 0.5 V,the refresh time was 10 s and 1000 s in multi-bit operation;these values were more than 150 and 15000 times longer than those of the conventional Si channel 1T1C DRAM,respectively.A monolithic stacked 2-line-based 2T0C DRAM was fabricated,and a multi-bit operation was confirmed.
文摘DRAM作为计算机存储系统的核心组件,在HPC、云计算、AI等领域至关重要。然而,传统1T1C DRAM受电容缩放瓶颈、刷新功耗及制造复杂度等问题限制,难以满足先进制程需求。2T0C DRAM采用双晶体管架构,利用浮体效应、栅极耦合等机制存储电荷,实现高密度、低功耗及工艺兼容性提升。本研究分析2T0C DRAM的技术原理、结构设计及其相较于1T1C DRAM的优势,探讨数据保持、读写干扰、工艺变异等挑战,并综述器件优化、电路创新及先进制造工艺的应对策略。此外,结合CIM、3D集成等趋势,探讨其在HPC、嵌入式及新型存储中的应用价值。当前,三星、美光等厂商已展开2T0C DRAM研发,预计未来逐步进入量产。随着半导体工艺演进,2T0C DRAM有望成为下一代高密度、低功耗存储技术。然而,量子效应、工艺适配及产业链完善仍是关键挑战。未来研究将聚焦器件微缩、存算一体及异质集成,推动2T0C DRAM发展与产业化进程。As a core component of computer memory systems, DRAM plays a critical role in HPC, cloud computing, and AI. However, traditional 1T1C DRAM faces challenges such as capacitor scaling limitations, high refresh power consumption, and increasing fabrication complexity, restricting its scalability in advanced process nodes. To address these issues, 2T0C DRAM adopts a two-transistor architecture, utilizing floating-body effects and gate coupling mechanisms to store charge, thereby enhancing storage density, reducing power consumption, and improving process compatibility. This study analyzes the technical principles and structural design of 2T0C DRAM, highlighting its advantages over 1T1C DRAM while addressing challenges such as data retention, read/write disturbances, and process variations. Various optimization strategies, including device engineering, circuit design innovations, and advanced fabrication techniques, are also reviewed. Furthermore, considering emerging trends like CIM and 3D integration, we explore the potential applications of 2T0C DRAM in HPC, embedded systems, and next-generation memory technologies. Currently, leading memory manufacturers such as Samsung and Micron have initiated research on 2T0C DRAM, with commercialization expected in the near future. With the continuous advancement of semiconductor technology, 2T0C DRAM is poised to become a key candidate for next-generation high-density, low-power memory solutions. However, challenges such as quantum effects, process adaptation, and supply chain maturity remain critical. Future research will focus on device scaling, in-memory computing, and heterogeneous integration to accelerate the development and industrialization of 2T0C DRAM.
文摘p53凋亡刺激蛋白2(apoptosis stimulating protein 2 of p53,ASPP2)能特异性地与p53蛋白结合并增强其促凋亡的功能,进而发挥抗肿瘤作用.本室前期研究发现,ASPP2可以通过p53-DRAM-自噬途径诱导细胞凋亡.在本研究中,利用ASPP2腺病毒感染Hep3B细胞(p53缺陷型肝癌细胞系)并用甲基磺酸(MMS)处理后;Calcein AM/PI和M30染色检测细胞凋亡;GFP-LC3质粒转染细胞后检测自噬;荧光定量PCR和免疫印迹检测自噬基因表达.结果表明,ASPP2在p53缺陷的Hep3B细胞内可诱导发生凋亡;在MMS存在和缺失条件下,Adr-ASPP2均引起自噬体水平升高及自噬基因的表达增加,且MMS协同Adr-ASPP2能使自噬水平增加;进一步用VPS34 siRNA和DRAM siRNA抑制自噬发现,细胞凋亡水平下降,说明由Adr-ASPP2诱发经损伤相关自噬调节蛋白(DRAM)介导的自噬参与了肝癌细胞系凋亡的发生.综上结果表明,ASPP2可以通过非p53依赖的DRAM介导自噬,并促进肝癌细胞凋亡.该研究可为肝癌的基因治疗提供新的思路.
