A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating b...A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilin- ear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier （OTA） is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of 0.04 mm2. At a 51.2 kS/s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 p J/step.展开更多
In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modu...In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modulator was proposed. It used a resonator based on Salo architecture,which employed doublesampling and double-delay technique. The results show that the proposed modulator can achieve lower power consumption and a lower capacitive load than the conventional bandpass modulators on the platform of Simulink. The circuit is implemented with TSMC0. 18 μm CMOS process and operates at a sampling frequency of 20 MHz, 80 MHz effective sampling frequency. Furthermore,it consumes 21. 2 mW from a 1. 8 V supply. The simulated peak signal-to-noise ratio( SNR) is 85. 9 dB and the dynamic range( DR) is 91 dB with 200 kHz bandwidth.展开更多
The logarithmic response complementary metal oxide semiconductor （CMOS） image sensor provides a wide dynamic range, but its drawback is the lack of simple fixed pattern noise（FPN） cancellation scheme. Designed is ...The logarithmic response complementary metal oxide semiconductor （CMOS） image sensor provides a wide dynamic range, but its drawback is the lack of simple fixed pattern noise（FPN） cancellation scheme. Designed is a novel logarithmic active pixel sensor（APS） with high dynamic range and high output swing. Firstly, the operation principle of mixed-model APS is introduced. The pixel can work in three operation modes by choosing the proper control signals. Then, FPN sources of logarithmic APS are analyzed, and double-sampled technique is implemented to reduce FPN. Finally, according to the simulation results, layout is designed and has passed design rule check（DRC）, electronic rule eheck（ERC） and layout versus schematic（LVS） verifications, and the post-simulation results are basically in agreement with the simulation results. Dynamic range of the new logarithmic APS can reach about 140 dB; and the output swing is about 750 inV. Results show that by using double sampled technique, most FPN is eliminated and the dynamic range is enhanced.展开更多
基金supported by the National High Technology Research and Development Program of China(No.2009AA042321)
文摘A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilin- ear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier （OTA） is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of 0.04 mm2. At a 51.2 kS/s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 p J/step.
基金Sponsored by the National Basic Research Program of China(Grant No.2012CB934104)
文摘In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modulator was proposed. It used a resonator based on Salo architecture,which employed doublesampling and double-delay technique. The results show that the proposed modulator can achieve lower power consumption and a lower capacitive load than the conventional bandpass modulators on the platform of Simulink. The circuit is implemented with TSMC0. 18 μm CMOS process and operates at a sampling frequency of 20 MHz, 80 MHz effective sampling frequency. Furthermore,it consumes 21. 2 mW from a 1. 8 V supply. The simulated peak signal-to-noise ratio( SNR) is 85. 9 dB and the dynamic range( DR) is 91 dB with 200 kHz bandwidth.
基金National Natural Science Foundation of China (60406003)Natural Science Foundation of Tianjin(08JCZDJC24100)
文摘The logarithmic response complementary metal oxide semiconductor （CMOS） image sensor provides a wide dynamic range, but its drawback is the lack of simple fixed pattern noise（FPN） cancellation scheme. Designed is a novel logarithmic active pixel sensor（APS） with high dynamic range and high output swing. Firstly, the operation principle of mixed-model APS is introduced. The pixel can work in three operation modes by choosing the proper control signals. Then, FPN sources of logarithmic APS are analyzed, and double-sampled technique is implemented to reduce FPN. Finally, according to the simulation results, layout is designed and has passed design rule check（DRC）, electronic rule eheck（ERC） and layout versus schematic（LVS） verifications, and the post-simulation results are basically in agreement with the simulation results. Dynamic range of the new logarithmic APS can reach about 140 dB; and the output swing is about 750 inV. Results show that by using double sampled technique, most FPN is eliminated and the dynamic range is enhanced.
