This paper presents a 4-level pulse amplitude modulation(PAM-4)distributed feedback(DFB)laser driver.The driver adopts a digital slicing architecture to achieve high linearity by adjusting the weights of three thermom...This paper presents a 4-level pulse amplitude modulation(PAM-4)distributed feedback(DFB)laser driver.The driver adopts a digital slicing architecture to achieve high linearity by adjusting the weights of three thermometer-coded main paths.An efficient-biased output stage structure is proposed to reduce power consumption while avoiding the degradation of out-put node bandwidth typically induced by parasitic capacitance in high-current bias path.A two-tap linear and nonlinear feed-for-ward equalizer(FFE)is implemented in the digital domain to extend bandwidth limitations and compensate for the dynamic nonlinearity of the DFB laser.The nonlinear FFE is realized at the cost of lower power consumption and smaller area by utiliz-ing the simultaneity of low-speed parallel data.The chip is fabricated in 28 nm CMOS process.Measurement results indicate that,with a laser bias current of 40 mA,a modulation current of 20 mApp,and an operating rate of 32 Gb/s PAM-4,the overall power consumption of the chip is 372 mW,corresponding to an energy efficiency of 11.6 pJ/b.展开更多
基金supported in part by Beijing Natural Science Foundation(Grant No.L247013)in part by the National Natural Science Foundation of China(Grant No.92373209)+1 种基金in part by Grant from the Chinese Academy of Sciences(Grant No.ZDBS-LY-JSC008)in part by Xiamen major science and technology project(Grant No.3502Z20221003).
文摘This paper presents a 4-level pulse amplitude modulation(PAM-4)distributed feedback(DFB)laser driver.The driver adopts a digital slicing architecture to achieve high linearity by adjusting the weights of three thermometer-coded main paths.An efficient-biased output stage structure is proposed to reduce power consumption while avoiding the degradation of out-put node bandwidth typically induced by parasitic capacitance in high-current bias path.A two-tap linear and nonlinear feed-for-ward equalizer(FFE)is implemented in the digital domain to extend bandwidth limitations and compensate for the dynamic nonlinearity of the DFB laser.The nonlinear FFE is realized at the cost of lower power consumption and smaller area by utiliz-ing the simultaneity of low-speed parallel data.The chip is fabricated in 28 nm CMOS process.Measurement results indicate that,with a laser bias current of 40 mA,a modulation current of 20 mApp,and an operating rate of 32 Gb/s PAM-4,the overall power consumption of the chip is 372 mW,corresponding to an energy efficiency of 11.6 pJ/b.
