This paper describes a complete baseband chain for both GSM and WCDMA receivers with a SMIC 0.35μm mixed signal process. The chain consists of a dual-mode,highly linear, fourth order Chebyshev active RC filter and th...This paper describes a complete baseband chain for both GSM and WCDMA receivers with a SMIC 0.35μm mixed signal process. The chain consists of a dual-mode,highly linear, fourth order Chebyshev active RC filter and three VGA stages. The filter is designed to meet the bandwidth specifications of the GSM and WCDMA standards and share the maximum number of components between the two modes to reduce manufacturing cost. The design is free of DC-offset and has an inter-stage high-pass filter, and operational amplifiers with adjustable GBW are used to minimize GSM-mode power consumption. The measured noise figures are 27. 3 and 42dBm in WCDMA and GSM modes,respectively, at the maximum gain. The IIP3 is 40dBm at unit gain in the WCDMA mode,and the circuit consumes 47.0mW. The IIP3 is 28dBm in the GSM mode,and the circuit consumes 31.8mW. The supply voltage is 3.3V.展开更多
A DC-offset cancellation scheme in a 5GHz direct-conversion receiver compliant with the IEEE 802.11a wireless LAN standard is presented. An analog feedback loop is used to eliminate the DC-offset at the output of the....A DC-offset cancellation scheme in a 5GHz direct-conversion receiver compliant with the IEEE 802.11a wireless LAN standard is presented. An analog feedback loop is used to eliminate the DC-offset at the output of the. double-balanced mixer. The test results show that the mixer with the DC-offset cancellation circuit has a voltage conversion gain of 9.5dB at 5.15GHz, a noise figure of 13.5dB, an IIP3 of 7.6dBm, a DC-offset voltage of 1.73mV eliminating 76% of DC-offset,and a power consumption of 67mW with a 3.3V supply. The direct conversion WLAN receiver has been implemented in 0.35μm SiGe BiCMOS technology.展开更多
This paper presents a broadband inductor-less variable gain amplifier （VGA） with a linear-in-dB gain control characteristic and DC-offset cancellation. The proposed VGA is composed of a variable gain block, an expon...This paper presents a broadband inductor-less variable gain amplifier （VGA） with a linear-in-dB gain control characteristic and DC-offset cancellation. The proposed VGA is composed of a variable gain block, an exponential voltage generator, a DC-offset canceller with common-mode voltage correction, and a gain peaking block. To achieve the broad band and reduce the chip area, the gain peaking block employs an inductor-less gain peaking scheme to compensate the high frequency gain drop of the variable gain block and the DC-offset canceller. The VGA fabricated in 0.13μm SiGe BiCMOS technology achieves a 3-dB bandwidth of 7.5 GHz and a variable gain range from -10 to 30 dB. Due to the inductor-less design, the die area is only 0.53 - 0.27 mm＆2 which is the smallest among other similar reported works. At 10-Gb/s, the VGA consumes 50 mW power from a single 1.2 V supply and exhibits an output data jitter of less than 30 pSpp.展开更多
A 2.4GHz monolithic CMOS receiver with direct-conversion architecture is presented. This quadrature receiver is designed for 802.11b wireless LAN applications at the maximum data rate of 11Mbps as a low-cost solution....A 2.4GHz monolithic CMOS receiver with direct-conversion architecture is presented. This quadrature receiver is designed for 802.11b wireless LAN applications at the maximum data rate of 11Mbps as a low-cost solution. Five key blocks,i, e., a low noise amplifier （LNA）, a down-conversion mixer, a variable gain amplifier, a low pass filter, and a DC- offset cancellation circuit,are designed based on system design and low noise high linearity considerations. The necessary auxiliary circuits are also included. Fabricated in SMIC 0.18μm 1p6m RF CMOS process, the receiver＇s performance is measured as：4. 1 dB noise figure, - 7.5dBm input third order intercept point （IIP3） for LNA ＆ mixer at high gain setting, - 14dBm IIP3 for the whole receiver,53dBc @30MHz offset of adjacent channel power rejection,and less than 5mV out- put DC-offset. The receiver consumes 44mA under a 1.8V power supply with I,Q two paths.展开更多
提出一种双自调谐二阶广义积分器锁频环(frequency-locked loop based on double self-tuning second ordergeneralized integrator,DSSOGI-FLL)同步方法,该方法将自调谐滤波器(self-tuning filter)与优化的SOGI两种结构相级联,构成一...提出一种双自调谐二阶广义积分器锁频环(frequency-locked loop based on double self-tuning second ordergeneralized integrator,DSSOGI-FLL)同步方法,该方法将自调谐滤波器(self-tuning filter)与优化的SOGI两种结构相级联,构成一种双自调谐二阶广义积分器(self-tuning second order generalized integrator,SSOGI),该结构具有较SOGI更佳的滤波能力;同时,通过引入求差节点和一阶高通滤波器,使其具备了消除直流分量的能力;最后,应用幅值归一化算法对锁频环(FLL)结构进行参数设计,达到易于数字化实现的效果。仿真与实验结果验证文中所提DSSOGI-FLL方法的可行性与有效性。展开更多
文摘This paper describes a complete baseband chain for both GSM and WCDMA receivers with a SMIC 0.35μm mixed signal process. The chain consists of a dual-mode,highly linear, fourth order Chebyshev active RC filter and three VGA stages. The filter is designed to meet the bandwidth specifications of the GSM and WCDMA standards and share the maximum number of components between the two modes to reduce manufacturing cost. The design is free of DC-offset and has an inter-stage high-pass filter, and operational amplifiers with adjustable GBW are used to minimize GSM-mode power consumption. The measured noise figures are 27. 3 and 42dBm in WCDMA and GSM modes,respectively, at the maximum gain. The IIP3 is 40dBm at unit gain in the WCDMA mode,and the circuit consumes 47.0mW. The IIP3 is 28dBm in the GSM mode,and the circuit consumes 31.8mW. The supply voltage is 3.3V.
文摘A DC-offset cancellation scheme in a 5GHz direct-conversion receiver compliant with the IEEE 802.11a wireless LAN standard is presented. An analog feedback loop is used to eliminate the DC-offset at the output of the. double-balanced mixer. The test results show that the mixer with the DC-offset cancellation circuit has a voltage conversion gain of 9.5dB at 5.15GHz, a noise figure of 13.5dB, an IIP3 of 7.6dBm, a DC-offset voltage of 1.73mV eliminating 76% of DC-offset,and a power consumption of 67mW with a 3.3V supply. The direct conversion WLAN receiver has been implemented in 0.35μm SiGe BiCMOS technology.
文摘This paper presents a broadband inductor-less variable gain amplifier （VGA） with a linear-in-dB gain control characteristic and DC-offset cancellation. The proposed VGA is composed of a variable gain block, an exponential voltage generator, a DC-offset canceller with common-mode voltage correction, and a gain peaking block. To achieve the broad band and reduce the chip area, the gain peaking block employs an inductor-less gain peaking scheme to compensate the high frequency gain drop of the variable gain block and the DC-offset canceller. The VGA fabricated in 0.13μm SiGe BiCMOS technology achieves a 3-dB bandwidth of 7.5 GHz and a variable gain range from -10 to 30 dB. Due to the inductor-less design, the die area is only 0.53 - 0.27 mm＆2 which is the smallest among other similar reported works. At 10-Gb/s, the VGA consumes 50 mW power from a single 1.2 V supply and exhibits an output data jitter of less than 30 pSpp.
基金the National Natural Science Foundation of China(No.60606009)~~
文摘A 2.4GHz monolithic CMOS receiver with direct-conversion architecture is presented. This quadrature receiver is designed for 802.11b wireless LAN applications at the maximum data rate of 11Mbps as a low-cost solution. Five key blocks,i, e., a low noise amplifier （LNA）, a down-conversion mixer, a variable gain amplifier, a low pass filter, and a DC- offset cancellation circuit,are designed based on system design and low noise high linearity considerations. The necessary auxiliary circuits are also included. Fabricated in SMIC 0.18μm 1p6m RF CMOS process, the receiver＇s performance is measured as：4. 1 dB noise figure, - 7.5dBm input third order intercept point （IIP3） for LNA ＆ mixer at high gain setting, - 14dBm IIP3 for the whole receiver,53dBc @30MHz offset of adjacent channel power rejection,and less than 5mV out- put DC-offset. The receiver consumes 44mA under a 1.8V power supply with I,Q two paths.
文摘提出一种双自调谐二阶广义积分器锁频环(frequency-locked loop based on double self-tuning second ordergeneralized integrator,DSSOGI-FLL)同步方法,该方法将自调谐滤波器(self-tuning filter)与优化的SOGI两种结构相级联,构成一种双自调谐二阶广义积分器(self-tuning second order generalized integrator,SSOGI),该结构具有较SOGI更佳的滤波能力;同时,通过引入求差节点和一阶高通滤波器,使其具备了消除直流分量的能力;最后,应用幅值归一化算法对锁频环(FLL)结构进行参数设计,达到易于数字化实现的效果。仿真与实验结果验证文中所提DSSOGI-FLL方法的可行性与有效性。
