This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,th...This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.展开更多
This paper proposes a baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness for use in the electronic toll collection system.A double-mode detection method,including amp...This paper proposes a baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness for use in the electronic toll collection system.A double-mode detection method,including amplitude detection and frequency detection,is proposed to reject interference and reduce false wake-ups.An improved closed-loop band-pass filter and a DC offset cancellation technique are also newly introduced to enhance the sensitivity robustness.The circuit is fabricated in TSMC 0.18μm 3.3 V CMOS technology with an area of 0.12 mm2.Measurement results show that the sensitivity is -54.5 dBm with only a±0.95 dBm variation from the 1.8 to 3.3 V power supply,and that the temperature variation of the sensitivity is±1.4 dBm from -50 to 100℃. The current consumption is 1.4 to 1.7μA under a 1.8 to 3.3 V power supply.展开更多
文摘This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.
基金supported by the National Natural Science Foundation of China(No.61106025)the National High Technology Research and Develop Program of China(No.2012AA012301)the National Science and Technology Major Project of China(No.2013ZX03006004)
文摘This paper proposes a baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness for use in the electronic toll collection system.A double-mode detection method,including amplitude detection and frequency detection,is proposed to reject interference and reduce false wake-ups.An improved closed-loop band-pass filter and a DC offset cancellation technique are also newly introduced to enhance the sensitivity robustness.The circuit is fabricated in TSMC 0.18μm 3.3 V CMOS technology with an area of 0.12 mm2.Measurement results show that the sensitivity is -54.5 dBm with only a±0.95 dBm variation from the 1.8 to 3.3 V power supply,and that the temperature variation of the sensitivity is±1.4 dBm from -50 to 100℃. The current consumption is 1.4 to 1.7μA under a 1.8 to 3.3 V power supply.
