This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit,...This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.展开更多
A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including ...A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA（RXPGA） provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA（TXPGA） covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA （I and Q path） under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC（DC offset cancellation） circuit shows 10 kHz of HPCF（high pass cutoff frequency） and the DCOC settling time is less than 0.45μs.展开更多
An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to...An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.展开更多
The bipolar low-voltage DC(LVDC) distribution system has become a prospective solution to better integration of renewables and improvement of system efficiency and reliability. However, it also faces the challenge of ...The bipolar low-voltage DC(LVDC) distribution system has become a prospective solution to better integration of renewables and improvement of system efficiency and reliability. However, it also faces the challenge of power and voltage imbalance between two poles. To solve this problem, an interface converter with bipolar asymmetrical operating capabilities is applied in this paper. The steady-state models of the bipolar LVDC distribution system equipped with this interface converter in the gridconnected mode and off-grid mode are analyzed. A control scheme based on DC offset injection at the secondary side of the interface converter is proposed, enabling the bipolar LVDC distribution system to realize the unbalanced power transfer between two poles in the grid-connected mode and maintain the inherentpole voltage balance in the off-grid mode. Furthermore, this paper also proposes a primary-side DC offset injection control scheme according to the analysis of the magnetic circuit model, which can eliminate the DC bias flux caused by the secondaryside DC offset. Thereby, the potential core magnetic saturation and overcurrent issues can be prevented, ensuring the safety of the interface converter and distribution system. Detailed simulations based on the proposed control scheme are conducted to validate the function of power and voltage balance under the operation conditions of different DC loads.展开更多
Fast and accurate monitoring of the phase,amplitude,and frequency of the grid voltage is essential for single-phase grid-connected converters.The presence of DC offset in the grid voltage is detrimental to not only gr...Fast and accurate monitoring of the phase,amplitude,and frequency of the grid voltage is essential for single-phase grid-connected converters.The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters.In this paper,a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation(ADSC)in a second-order generalized integrator(SOGI)phase-locked loop(PLL).A frequency-fixed SOGI-based PLL(FFSOGI-PLL)is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs.A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral(PI)controller gains.The effects of frequency variation and ADSC on the proposed PLL are considered,and correction methods are adopted to accurately estimate grid information.The simulation results are presented,along with comparisons to other single-phase PLLs in terms of settling time,peak frequency,and phase error to validate the proposed PLL.The dynamic performance of the proposed PLL is also experimentally validated.Overall,the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices,offering an improved solution for precise grid synchronization in single-phase applications.展开更多
This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,th...This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.展开更多
A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage reje...A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications. The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing. The calibration loop achieves constant high-pass pole when gain changes; and a fast response time by programming the pole to 1 MHz during preamble and to 30 kHz during receiving data. The transmitter baseband employs an auto-calibration loop with on-chip AD and DA to suppress the carrier leakage, and AD can be powered down after calibration to save power consumption. The chip consumes 17.52 mA for RX baseband VGA and DCOC, and 8.3 mA for TX carrier leakage calibration （5.88 mA after calibration） from 2.85 V supply. Implemented in a 0.35μm SiGe technology, they occupy 0.68 mm^2 and 0.18 mma die size respectively.展开更多
A low power mixed signal DC offset calibration （DCOC） circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die a...A low power mixed signal DC offset calibration （DCOC） circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 ×0.419 mm^2.展开更多
A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based techniqu...A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier（PGA） can be converted to an analog controlled dB-linear VGA. An operational amplifier（OPAMP） utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation（DCOC） loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm^2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency（HPCF） and the measured residual DC offset at the output of VGA is less than 2 mV.展开更多
A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offse...A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offset rejection scheme, the IC achieves lower offset voltage and lower power consumption compared to previous designs. This configuration rejects large DC offset and drift that exist at the skin-electrode interface without the need of external components. The proposed amplifier has been implemented in SMIC 0.18-μm 1P6M CMOS technol-ogy, with an active silicon area of 100 μm by 120 μm. The back-annotated simulation results demonstrated the circuit features the systematic offset voltage less than 80 μV, the offset drift about 0.27 μV/℃ for temperature ranging from –30℃ to 100℃ and the total power dissipation consumed as low as 37.8 μW from a 1.8 V single supply. It dedicated to monitor low amplitude biomedical signals recording.展开更多
基金Supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2012ZX03004008)
文摘This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.
文摘A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA（RXPGA） provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA（TXPGA） covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA （I and Q path） under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC（DC offset cancellation） circuit shows 10 kHz of HPCF（high pass cutoff frequency） and the DCOC settling time is less than 0.45μs.
基金Project supported by the Major Projects for the Core Electronic Devices,High-End General Chips and Basic Software Products(No. 2009ZX01031-002-008)
文摘An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.
基金supported by the National Natural Science Foundation of China (No. 51877136)the Shanghai Committee of Science and Technology (No. 19DZ1205403)the Inner Mongolia Autonomous Region Committee of Science and Technology (No. 2020GG0299)。
文摘The bipolar low-voltage DC(LVDC) distribution system has become a prospective solution to better integration of renewables and improvement of system efficiency and reliability. However, it also faces the challenge of power and voltage imbalance between two poles. To solve this problem, an interface converter with bipolar asymmetrical operating capabilities is applied in this paper. The steady-state models of the bipolar LVDC distribution system equipped with this interface converter in the gridconnected mode and off-grid mode are analyzed. A control scheme based on DC offset injection at the secondary side of the interface converter is proposed, enabling the bipolar LVDC distribution system to realize the unbalanced power transfer between two poles in the grid-connected mode and maintain the inherentpole voltage balance in the off-grid mode. Furthermore, this paper also proposes a primary-side DC offset injection control scheme according to the analysis of the magnetic circuit model, which can eliminate the DC bias flux caused by the secondaryside DC offset. Thereby, the potential core magnetic saturation and overcurrent issues can be prevented, ensuring the safety of the interface converter and distribution system. Detailed simulations based on the proposed control scheme are conducted to validate the function of power and voltage balance under the operation conditions of different DC loads.
基金supported by the Deanship of Research at Jordan University of Science and Technology (Grant number:20210333).
文摘Fast and accurate monitoring of the phase,amplitude,and frequency of the grid voltage is essential for single-phase grid-connected converters.The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters.In this paper,a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation(ADSC)in a second-order generalized integrator(SOGI)phase-locked loop(PLL).A frequency-fixed SOGI-based PLL(FFSOGI-PLL)is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs.A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral(PI)controller gains.The effects of frequency variation and ADSC on the proposed PLL are considered,and correction methods are adopted to accurately estimate grid information.The simulation results are presented,along with comparisons to other single-phase PLLs in terms of settling time,peak frequency,and phase error to validate the proposed PLL.The dynamic performance of the proposed PLL is also experimentally validated.Overall,the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices,offering an improved solution for precise grid synchronization in single-phase applications.
文摘This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.
文摘A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications. The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing. The calibration loop achieves constant high-pass pole when gain changes; and a fast response time by programming the pole to 1 MHz during preamble and to 30 kHz during receiving data. The transmitter baseband employs an auto-calibration loop with on-chip AD and DA to suppress the carrier leakage, and AD can be powered down after calibration to save power consumption. The chip consumes 17.52 mA for RX baseband VGA and DCOC, and 8.3 mA for TX carrier leakage calibration （5.88 mA after calibration） from 2.85 V supply. Implemented in a 0.35μm SiGe technology, they occupy 0.68 mm^2 and 0.18 mma die size respectively.
文摘A low power mixed signal DC offset calibration （DCOC） circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 ×0.419 mm^2.
文摘A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier（PGA） can be converted to an analog controlled dB-linear VGA. An operational amplifier（OPAMP） utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation（DCOC） loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm^2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency（HPCF） and the measured residual DC offset at the output of VGA is less than 2 mV.
文摘A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offset rejection scheme, the IC achieves lower offset voltage and lower power consumption compared to previous designs. This configuration rejects large DC offset and drift that exist at the skin-electrode interface without the need of external components. The proposed amplifier has been implemented in SMIC 0.18-μm 1P6M CMOS technol-ogy, with an active silicon area of 100 μm by 120 μm. The back-annotated simulation results demonstrated the circuit features the systematic offset voltage less than 80 μV, the offset drift about 0.27 μV/℃ for temperature ranging from –30℃ to 100℃ and the total power dissipation consumed as low as 37.8 μW from a 1.8 V single supply. It dedicated to monitor low amplitude biomedical signals recording.
