The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically ab...The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically about 30% to 70% of the total dynamic (switching) power consumption. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. In this work, a new methodology is applied for gating the Flip flop by which the power will be reduced. The clock gating is employed to the pipelining stage flip flop which is active only during valid data are arrived. The methodology used in project named Selective Look-Ahead Clock Gating computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. Similarly to data-driven gating, it is capable of stopping the majority of redundant clock pulses. In this work, the circuit implementation of the various blocks of data driven clock gating is done and the results are observed. The proposed work is used for pipelining stage in microprocessor and DSP architectures. The proposed method is simulated using the quartus for cyclone 3 kit.展开更多
We propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes the advantages of mesh and tree architectures.The problems of skew reduction and variation-tolerance...We propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes the advantages of mesh and tree architectures.The problems of skew reduction and variation-tolerance in the mixed interconnection network are studied through a pipelined multiplier under a TSMC 65 nm standard CMOS process.The post-simulation results show that the hierarchical architecture reduces more than 75% and 65%of clock skew compared with pure mesh and pure H-tree networks,respectively.The maximum skew in the proposed clock distribution is less than 7 ps under imbalanced loading and PVT variations,which is no more than 1%of the clock cycle of about 760 ps.展开更多
Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consump...Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actually strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result, incremental modifications are performed based on the clock skew specifications by moving registers toward preferred locations that may reduce the clock network size. At the same time, the side-effects to logic cell placement, such as signal net wirelength and critical path delay, are controlled. Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.展开更多
The BaF2 （barium fluoride） spectrometer is one of the experiment facilities at the CSNS-WNS（White Neutron Source at China Spallation Neutron Source）, currently under construction. It is designed to precisely measu...The BaF2 （barium fluoride） spectrometer is one of the experiment facilities at the CSNS-WNS（White Neutron Source at China Spallation Neutron Source）, currently under construction. It is designed to precisely measure the（n, γ） cross section, with 92 crystal elements and complete 4π steradian coverage. In order to improve the precision of measurement, in this paper, a new precise digitization and readout method is proposed. Waveform digitizing with 1 GSps sampling rate and 12-bit resolution is used to precisely capture the detector signal. To solve the problem of massive data readout and processing, the readout electronics is designed as a distributed architecture with 4 PXIe crates. The digitized signal is concentrated to the PXIe crate controller through a PCIe bus on the backplane and transmitted to the data acquisition system over gigabit Ethernet in parallel. Besides, the clock and trigger can be fanned out synchronously to every electronic channel over a high-precision distribution network. Test results show that the prototype of the readout electronics can achieve good performance and meet the requirements of the CSNS-WNS BaF2 spectrometer.展开更多
文摘The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically about 30% to 70% of the total dynamic (switching) power consumption. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. In this work, a new methodology is applied for gating the Flip flop by which the power will be reduced. The clock gating is employed to the pipelining stage flip flop which is active only during valid data are arrived. The methodology used in project named Selective Look-Ahead Clock Gating computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. Similarly to data-driven gating, it is capable of stopping the majority of redundant clock pulses. In this work, the circuit implementation of the various blocks of data driven clock gating is done and the results are observed. The proposed work is used for pipelining stage in microprocessor and DSP architectures. The proposed method is simulated using the quartus for cyclone 3 kit.
基金Project supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No. 2009ZX01034-001-001-006)the National Natural Science Foundation of China(No.60906014)
文摘We propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes the advantages of mesh and tree architectures.The problems of skew reduction and variation-tolerance in the mixed interconnection network are studied through a pipelined multiplier under a TSMC 65 nm standard CMOS process.The post-simulation results show that the hierarchical architecture reduces more than 75% and 65%of clock skew compared with pure mesh and pure H-tree networks,respectively.The maximum skew in the proposed clock distribution is less than 7 ps under imbalanced loading and PVT variations,which is no more than 1%of the clock cycle of about 760 ps.
基金the National Natural Science Foundation of China (No. 60776026)
文摘Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actually strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result, incremental modifications are performed based on the clock skew specifications by moving registers toward preferred locations that may reduce the clock network size. At the same time, the side-effects to logic cell placement, such as signal net wirelength and critical path delay, are controlled. Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.
基金Supported by National Research and Development plan(2016YFA0401602)NSAF(U1530111)
文摘The BaF2 （barium fluoride） spectrometer is one of the experiment facilities at the CSNS-WNS（White Neutron Source at China Spallation Neutron Source）, currently under construction. It is designed to precisely measure the（n, γ） cross section, with 92 crystal elements and complete 4π steradian coverage. In order to improve the precision of measurement, in this paper, a new precise digitization and readout method is proposed. Waveform digitizing with 1 GSps sampling rate and 12-bit resolution is used to precisely capture the detector signal. To solve the problem of massive data readout and processing, the readout electronics is designed as a distributed architecture with 4 PXIe crates. The digitized signal is concentrated to the PXIe crate controller through a PCIe bus on the backplane and transmitted to the data acquisition system over gigabit Ethernet in parallel. Besides, the clock and trigger can be fanned out synchronously to every electronic channel over a high-precision distribution network. Test results show that the prototype of the readout electronics can achieve good performance and meet the requirements of the CSNS-WNS BaF2 spectrometer.
