Against the backdrop of the strategy to build a manufacturing powerhouse and the rapid development of integrated circuits(ICs),the emergence of new technologies,materials,and processes has rendered traditional IC reli...Against the backdrop of the strategy to build a manufacturing powerhouse and the rapid development of integrated circuits(ICs),the emergence of new technologies,materials,and processes has rendered traditional IC reliability techniques inadequate for the evolving needs of IC development.Addressing the construction of an innovative IC reliability experiment platform has become a critical issue for scientific researchers at our city’s universities.This paper takes the Shenyang branch of the National Special Computer Research Center as a case study to explore how to optimize the construction of an IC reliability innovation platform.The discussion is structured around three dimensions:expanding the platform’s application scope,enhancing talent capabilities,and improving technological innovation levels.The findings are instrumental in elevating the standard of innovation platforms within the city.展开更多
To effectively tolerate a double-node upset,a novel double-node-upset-resilient radiation-hardened latch is proposed in 22 nm complementary-metal-oxide-semiconductor technology.Using three interlocked single-node-upse...To effectively tolerate a double-node upset,a novel double-node-upset-resilient radiation-hardened latch is proposed in 22 nm complementary-metal-oxide-semiconductor technology.Using three interlocked single-node-upset-resilient cells,which are identically mainly constructed from three mutually feeding back 2-input C-elements,the latch achieves double-node-upset-resilience.Using smaller transistor sizes,clock-gating technology,and high-speed transmission-path,the cost of the latch is effectively reduced.Simulation results demonstrate the double-node-upset-resilience of the latch and also show that compared with the up-to-date double-node-upset-resilient latches,the proposed latch reduces the transmission delay by 72.54%,the power dissipation by 33.97%,and the delay-power-area product by 78.57%,while the average cost of the silicon area is only increased by 16.45%.展开更多
With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Curren...With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.展开更多
Hardening reliability-critical gates in a circuit is an important step to improve the circuit reliability at a low cost.However,accurately locating the reliability-critical gates is a key prerequisite for the efficien...Hardening reliability-critical gates in a circuit is an important step to improve the circuit reliability at a low cost.However,accurately locating the reliability-critical gates is a key prerequisite for the efficient implementation of the hardening operation.In this paper,a probabilistic-based calculation method developed for locating the reliabilitycritical gates in a circuit is described.The proposed method is based on the generation of input vectors and the sampling of reliability-critical gates using uniform non-Bernoulli sequences,and the criticality of the gate reliability is measured by combining the structure information of the circuit itself.Both the accuracy and the efficiency of the proposed method have been illustrated by various simulations on benchmark circuits.The results show that the proposed method has an efficient performance in locating accuracy and algorithm runtime.展开更多
文摘Against the backdrop of the strategy to build a manufacturing powerhouse and the rapid development of integrated circuits(ICs),the emergence of new technologies,materials,and processes has rendered traditional IC reliability techniques inadequate for the evolving needs of IC development.Addressing the construction of an innovative IC reliability experiment platform has become a critical issue for scientific researchers at our city’s universities.This paper takes the Shenyang branch of the National Special Computer Research Center as a case study to explore how to optimize the construction of an IC reliability innovation platform.The discussion is structured around three dimensions:expanding the platform’s application scope,enhancing talent capabilities,and improving technological innovation levels.The findings are instrumental in elevating the standard of innovation platforms within the city.
基金The National Natural Science Foundation of China(No.61604001)the Doctor Startup Fund of Anhui University(No.J01003217)
文摘To effectively tolerate a double-node upset,a novel double-node-upset-resilient radiation-hardened latch is proposed in 22 nm complementary-metal-oxide-semiconductor technology.Using three interlocked single-node-upset-resilient cells,which are identically mainly constructed from three mutually feeding back 2-input C-elements,the latch achieves double-node-upset-resilience.Using smaller transistor sizes,clock-gating technology,and high-speed transmission-path,the cost of the latch is effectively reduced.Simulation results demonstrate the double-node-upset-resilience of the latch and also show that compared with the up-to-date double-node-upset-resilient latches,the proposed latch reduces the transmission delay by 72.54%,the power dissipation by 33.97%,and the delay-power-area product by 78.57%,while the average cost of the silicon area is only increased by 16.45%.
基金The Open Project Program of the Shanxi Key Laboratory of Advanced Semiconductor Optoelectronic Devices and Integrated Systems(2023SZKF17)the University Synergy Innovation Program of Anhui Province(GXXT-2022-080)。
文摘With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.
基金supported by the National Natural Science Foundation of China(Nos.61972354,61432017,61772199,61802347,and 61503338)the Natural Science Foundation of Zhejiang Province(Nos.LY18F020028 and LY18F030023)the Innovative Experiment Project of Zhejiang University of Technology(No.PX-68182112)。
文摘Hardening reliability-critical gates in a circuit is an important step to improve the circuit reliability at a low cost.However,accurately locating the reliability-critical gates is a key prerequisite for the efficient implementation of the hardening operation.In this paper,a probabilistic-based calculation method developed for locating the reliabilitycritical gates in a circuit is described.The proposed method is based on the generation of input vectors and the sampling of reliability-critical gates using uniform non-Bernoulli sequences,and the criticality of the gate reliability is measured by combining the structure information of the circuit itself.Both the accuracy and the efficiency of the proposed method have been illustrated by various simulations on benchmark circuits.The results show that the proposed method has an efficient performance in locating accuracy and algorithm runtime.
