Multiple-access interference(MAI) and beat noise(BN) in chip-asynchronous coherent time-spreading OCDMA system are evaluated by the aperiodic cross-correlation function of up-sampled sequence.Relationship between the ...Multiple-access interference(MAI) and beat noise(BN) in chip-asynchronous coherent time-spreading OCDMA system are evaluated by the aperiodic cross-correlation function of up-sampled sequence.Relationship between the mean intensity of aperiodic cross-correlation and MAI and BN is deduced,and then the relationship between BER and mean intensity of aperiodic cross-correlation is discussed.For 127-long gold sequence,mean BER performance of chip-asynchronous coherent time-spreading OCDMA is derived and compared...展开更多
This paper considers blind chip rate estimation of DS-SS signals in multi-rate and multi-user DS-CDMA systems over channels having slow flat Rayleigh fading plus additive white Gaussian noise. Channel impulse response...This paper considers blind chip rate estimation of DS-SS signals in multi-rate and multi-user DS-CDMA systems over channels having slow flat Rayleigh fading plus additive white Gaussian noise. Channel impulse response is estimated by a subspace method, and then the chip rate of each signal is estimated using zero crossing of estimated differential channel impulse response. For chip rate estimation of each user, an algorithm which uses weighted zero-crossing ratio is proposed. Maximum value of the weighted zero crossing ratio takes place in the Nyquist rate sampling frequency, which equals to the twice of the chip rate. Furthermore, bit time of each user is estimated using fluctuations of autocorrelation estimators. Since code length of each user can be obtained using bit time and chip time ratio. Fading channels reduce reliability factor of the proposed algo-rithm. To overcome this problem, a receiver with multiple antennas is proposed, and the reliability factor of the proposed algorithm is analyzed over both spatially correlated and independent fading channels.展开更多
The study was conducted to evaluate the effect of baking conditions of partially-dried potato slices (PDPS) prior baking on the quality attributes of the resultant baked potato chips. Baking experiment was conducted a...The study was conducted to evaluate the effect of baking conditions of partially-dried potato slices (PDPS) prior baking on the quality attributes of the resultant baked potato chips. Baking experiment was conducted at power levels of 80 and 100 Watts for different baking times according to microwave power used. Texture, color measurements and sensory evaluation were carried out on resultant baked potato chips. The results showed that partially drying step (even to 40% moisture content) prior microwave baking resulted in marked crispiness as well as brilliant yellow in resultant potato chips. The optimum conditions for the best quality of partially-dried potato chips were microwave cooking at power level of 100 Watts for 100 seconds.展开更多
A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test an...A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.展开更多
A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarith...A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.展开更多
基金supported by the National Natural Science Foundation of China (No.60772027)
文摘Multiple-access interference(MAI) and beat noise(BN) in chip-asynchronous coherent time-spreading OCDMA system are evaluated by the aperiodic cross-correlation function of up-sampled sequence.Relationship between the mean intensity of aperiodic cross-correlation and MAI and BN is deduced,and then the relationship between BER and mean intensity of aperiodic cross-correlation is discussed.For 127-long gold sequence,mean BER performance of chip-asynchronous coherent time-spreading OCDMA is derived and compared...
文摘This paper considers blind chip rate estimation of DS-SS signals in multi-rate and multi-user DS-CDMA systems over channels having slow flat Rayleigh fading plus additive white Gaussian noise. Channel impulse response is estimated by a subspace method, and then the chip rate of each signal is estimated using zero crossing of estimated differential channel impulse response. For chip rate estimation of each user, an algorithm which uses weighted zero-crossing ratio is proposed. Maximum value of the weighted zero crossing ratio takes place in the Nyquist rate sampling frequency, which equals to the twice of the chip rate. Furthermore, bit time of each user is estimated using fluctuations of autocorrelation estimators. Since code length of each user can be obtained using bit time and chip time ratio. Fading channels reduce reliability factor of the proposed algo-rithm. To overcome this problem, a receiver with multiple antennas is proposed, and the reliability factor of the proposed algorithm is analyzed over both spatially correlated and independent fading channels.
文摘The study was conducted to evaluate the effect of baking conditions of partially-dried potato slices (PDPS) prior baking on the quality attributes of the resultant baked potato chips. Baking experiment was conducted at power levels of 80 and 100 Watts for different baking times according to microwave power used. Texture, color measurements and sensory evaluation were carried out on resultant baked potato chips. The results showed that partially drying step (even to 40% moisture content) prior microwave baking resulted in marked crispiness as well as brilliant yellow in resultant potato chips. The optimum conditions for the best quality of partially-dried potato chips were microwave cooking at power level of 100 Watts for 100 seconds.
基金Project supported by the SDC Project of Science and Technology Commission of Shanghai Municipality (Grant No.08706201000)the AM Foundation Project of Science and Technology Commission of Shanghai Municipality (Grant No.08700741000)+1 种基金the Leading Academic Discipline Project of Shanghai Education Commission (Grant No.J50104)the Innovation Foundation Project of Shanghai University
文摘A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.
文摘A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.
