The atomically thin nature of two-dimensional(2D)layered materials makes them susceptible to charge trapping by randomly created disorders,adversely affecting carrier dynamics such as charge transport and exciton life...The atomically thin nature of two-dimensional(2D)layered materials makes them susceptible to charge trapping by randomly created disorders,adversely affecting carrier dynamics such as charge transport and exciton lifetime.Typically,these disorders lead to poor device performance or require additional space to mitigate performance degradation.In this study,we investigate 2D layered Dion–Jacobson(DJ)-phase oxide perovskite nanosheets,which exhibit charge trapping within their well-defined quantum well(QW)structures,resulting in unique tailoring of electrical conductivity and photoconductivity.These DJ-phase perovskites,composed of tunable atomic constituents,demonstrate resonant tunneling and anomalous charge trapping due to their ultra-clean QWs.Remarkably,the conductivity of insulating HSr_(2)Nb_(3)O_(10)(HSNO)increased over 1000 times upon applying voltage without additional treatments.We observed persistent photoconductivity in 2D vertical heterostructure devices,attributed to charge trapping in QWs,and demonstrated artificial synaptic behaviours in a single flake with tailored energy consumption.Varying the number of perovskite layers significantly allows the tunability of the energy bandgap.This study also highlights the high tunability of 2D perovskite nanosheets,promising various applications,including magnetic,high-k dielectric,and resistive switching devices.Our findings suggest a new class of ionic layered materials with great potential as novel two-dimensional building blocks for device applications.展开更多
In this paper, we investigate an Al2O3/HfSiO stack as the blocking layer of a metal-oxide-nitride-oxide-silicon- type （MONOS） memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the block...In this paper, we investigate an Al2O3/HfSiO stack as the blocking layer of a metal-oxide-nitride-oxide-silicon- type （MONOS） memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the blocking layer or an Al2O3/HfO2 stack as the blocking layer, the sample with the Al2O3/HfSiO stack as the blocking layer shows high program/erase （P/E） speed and good data retention characteristics. These improved performances can be explained by energy band engineering. The experimental results demonstrate that the memory device with an Al2O3/HfSiO stack as the blocking layer has great potential for further high-performance nonvolatile memory applications.展开更多
Because of the discrete charge storage mechanism, charge trapping memory（CTM） technique is a good candidate for aerospace and military missions. The total ionization dose（TID） effects on CTM cells with Al2O3/HfO2/...Because of the discrete charge storage mechanism, charge trapping memory（CTM） technique is a good candidate for aerospace and military missions. The total ionization dose（TID） effects on CTM cells with Al2O3/HfO2/Al2O3（AHA） high-k gate stack structure under in-situ 10 keV x-rays are studied. The C-V characteristics at different radiation doses demonstrate that charge stored in the device continues to be leaked away during the irradiation,thereby inducing the shift of flat band voltage（V（fb））. The dc memory window shows insignificant changes, suggesting the existence of good P/E ability. Furthermore, the physical mechanisms of TID induced radiation damages in AHA-based CTM are analyzed.展开更多
Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured...Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope(XPS) and transmission electron microscope(TEM)measurements. In addition, Rutherford back scattering(RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer.展开更多
This paper utilizes multilayer organic light-emitting diodes with a thin layer of dye molecules to study the mech- anism of charge trapping under different electric regimes. It demonstrates that the carrier trapping w...This paper utilizes multilayer organic light-emitting diodes with a thin layer of dye molecules to study the mech- anism of charge trapping under different electric regimes. It demonstrates that the carrier trapping was independent of the current density in devices using fluorescent material as the emitting molecule while this process was exactly opposite when phosphorescent material was used. The triplet-triplet annihilation and dissociation of excitons into free charge carriers was considered to contribute to the decrease in phosphorescent emission under high electric fields. Moreover, the fluorescent dye molecule with a lower energy gap and ionized potential than the host emitter was observed to facilitate the carrier trapping mechanism, and it would produce photon emission.展开更多
Charge trapping devices incorporating 2D materials and high-κdielectrics have emerged as promising candidates for compact,multifunctional memory devices compatible with silicon-based manufacturing processes.However,t...Charge trapping devices incorporating 2D materials and high-κdielectrics have emerged as promising candidates for compact,multifunctional memory devices compatible with silicon-based manufacturing processes.However,traditional charge trapping devices encounter bottlenecks including complex device structure and low operation speed.Here,we demonstrate an ultrafast reconfigurable direct charge trapping device utilizing only a 30 nm-thick Al_(2)O_(3)trapping layer with a MoS_(2)channel,where charge traps reside within the Al_(2)O_(3)bulk confirmed by transfer curves with different gatevoltage sweeping rates and photoluminescence(PL)spectra.The direct charging tapping device shows exceptional memory performance in both three-terminal and two-terminal operation modes characterized by ultrafast three-terminal operation speed(~300 ns),an extremely low OFF current of 10^(-14)A,a high ON/OFF current ratio of up to 10^(7),and stable retention and endurance properties.Furthermore,the device with a simple symmetrical structure exhibits VDpolarity-dependent reverse rectification behavior in the high resistance state(HRS),with a rectification ratio of 10^(5).Additionally,utilizing the synergistic modulation of the conductance of the MoS_(2)channel by V_(D)and V_(G),it achieves gate-tunable reverse rectifier and ternary logic capabilities.展开更多
We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the phy...We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect,we first establish a model to simulate the electron trapping behavior in n-type Si FeFET.The model is based on the quantum mechanical electron tunneling theory.And then,we use the pulsed I_d-V_g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET.Our model fits the experimental data well.By fitting the model with the experimental data,we get the following conclusions.(i)During the positive operation pulse,electrons in the Si substrate are mainly trapped at the interface between the ferroelectric(FE)layer and interlayer(IL)of the FeFET gate stack by inelastic trap-assisted tunneling.(ii)Based on our model,we can get the number of electrons trapped into the gate stack during the positive operation pulse.(iii)The model can be used to evaluate trap parameters,which will help us to further understand the fatigue mechanism of FeFET.展开更多
Impact of band-engineering to the performance of charge trapping memory with HfO2/Ta2O5/HfO2 （HTH） as the charge trapping layer is investigated. Compared with devices with the same total HfO2 thickness, structures w...Impact of band-engineering to the performance of charge trapping memory with HfO2/Ta2O5/HfO2 （HTH） as the charge trapping layer is investigated. Compared with devices with the same total HfO2 thickness, structures with Ta2O5 closer to substrates show larger program/erase window, because the 2nd HfO2 （next to blocking oxide） serving as part of blocking oxide reduces the current tunneling out of/in the charge trapping layer during program and erase. Moreover, trapped charge centroid is modulated and contributed more to the fiat-band voltage shift. Further experiments prove that devices with a thicker 2nd HfO2 layer exhibit larger saturate fiat-band shift in both program and erase operation. The optimized device achieves a 7 V memory window and good reliability characteristics.展开更多
Heavy ion irradiation effects on charge trapping memory(CTM)capacitors with TiN/Al_(2)O_(3)/HfO_(2)/Al_(2)O_(3)/HfO_(2)/SiO_(2)/p-Si structure have been investigated.The ion-induced interface charges and oxide trap ch...Heavy ion irradiation effects on charge trapping memory(CTM)capacitors with TiN/Al_(2)O_(3)/HfO_(2)/Al_(2)O_(3)/HfO_(2)/SiO_(2)/p-Si structure have been investigated.The ion-induced interface charges and oxide trap charges were calculated and analyzed by capacitance-voltage(C-V)characteristics.The C-V curves shift towards the negative direction after swift heavy ion irradiation,due to the net positive charges accumulating in the trapping layer.The memory window decreases with the increase of ion fluence at high voltage,which results from heavy ion-induced structural damage in the blocking layer.The mechanism of heavy ion irradiation effects on CTM capacitors is discussed in detail with energy band diagrams.The results may help to better understand the physical mechanism of heavy ion-induced degradation of CTM capacitors.展开更多
Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Co...Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.展开更多
We have evaluated the effects of recombination processes in a charge storage layer, either between trapped electrons and trapped holes or between trapped carriers and free carriers, on charge trapping memory cell＇s p...We have evaluated the effects of recombination processes in a charge storage layer, either between trapped electrons and trapped holes or between trapped carriers and free carriers, on charge trapping memory cell＇s performances by numerical simulation. Recombination is an indispensable mechanism in charge trapping memory. It helps charge convert process between negative and positive charges in the charge storage layer during charge trapping memory programming/erasing operation. It can affect the speed of programming and erasing operations.展开更多
In this work, the trap-assisted tunneling（TAT） mechanism is modeled as a two-step physical process for charge trapping memory（CTM）. The influence of the TAT mechanism on CTM performance is investigated in consider...In this work, the trap-assisted tunneling（TAT） mechanism is modeled as a two-step physical process for charge trapping memory（CTM）. The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.展开更多
We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random ...We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO_(2) interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 10^(12) cm^(–2) and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.展开更多
We evaluate the influence of the thermally assisted tunneling （TAT） mechanism on charge trapping memory （CTM） cell performance by numerical simulation, and comprehensively analyse the effects of the temperature, t...We evaluate the influence of the thermally assisted tunneling （TAT） mechanism on charge trapping memory （CTM） cell performance by numerical simulation, and comprehensively analyse the effects of the temperature, trap depth, distribution of trapped charge, gate voltage and parameters of TAT on erasing/programming speed and retention performance. TAT is an indispensable mechanism in CTM that can increase the detrapping probability of trapped charge. Our results reveal that the TAT effect causes the sensitivity of cell performance to temperature and it could affect the operational speed, especially for the erasing operation. The results show that the retention performance degrades compared with when the TAT mechanism is ignored.展开更多
We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent pr...We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.展开更多
OFET-type optical memories using light bias as the fourth terminal enable low voltage electrical stresses to suffice in generating substantial memory window and photoassisted multibit storage.The undefined molecular s...OFET-type optical memories using light bias as the fourth terminal enable low voltage electrical stresses to suffice in generating substantial memory window and photoassisted multibit storage.The undefined molecular structure and trapping mechanism of most storage media limit their practical applications.Herein,we report a series of charge trapping materials with the rigid and planar conjugated structure of benzo[1,2-b:4,5-b’]dithiophene(BDT)acting as the charge trapping site and photoresponsive group,while the insulated(triisopropylsilyl)acetylene(TIPS)unit is introduced to prevent the leakage path of the charge.The pentacene-based OFET memory with solution-processing TTIPS-BDT shows fast trapping speed,tunable ambipolar memory,large memory window and reliable charge retention,which is obviously improved compare to the performance of BDT and DTIPS-BDT devices.In addition,the charge trapping,memory characteristics and photoresponsive behaviors are also discussed in detail.The TTIPS-BDT device shows a specific response to green light illumination.This study suggests that BDT derivatives serving as charge trapping elements possess potential applications in future photoresponsive memory and plastic electronics.展开更多
We have investigated the effect of post deposition annealing (PDA) temperature of Al2O3 blocking layer on the performance of charge trapping memory capacitors. Two splits of PDA were performed in N2 ambient at 850...We have investigated the effect of post deposition annealing (PDA) temperature of Al2O3 blocking layer on the performance of charge trapping memory capacitors. Two splits of PDA were performed in N2 ambient at 850°C/60 s and 1050°C/60 s, respectively. The 1050°C annealed capacitor could be programmed and erased normally by using Fowler-Nordheim (FN) injection. In contrast, the 850°C annealed device could not be erased, even though it could be programmed properly. By measuring the gate leakage current and the flatband voltage shift, we found the erase failure in the 850°C annealed device was due to a larger gate back-injection leakage current at Vg<0. The trend of gate leakage current was further verified in two Al/Al2O3/SiO2/p-Si control capacitors with the same PDA splits. In addition, constant voltage stress measurements on control capacitors in the FN regime showed that the change of gate leakage current followed an empirical Curie-von Schweidler law at Vg<0. The data pointed out the importance to further study the relation between PDA conditions and the defect generation properties in Al2O3 blocking layer.展开更多
This work presents a self-consistent two-dimensional(2-D) simulation method with unified physical models for different operation regimes of charge trapping memory. The simulation carefully takes into consideration the...This work presents a self-consistent two-dimensional(2-D) simulation method with unified physical models for different operation regimes of charge trapping memory. The simulation carefully takes into consideration the tunneling process, charge trapping/de-trapping mechanisms, and 2-D drift-diffusion transport within the storage layer. A string of three memory cells has been simulated and evaluated for different gate stack compositions and temperatures. The simulator is able to describe the charge transport behavior along bitline and tunneling directions under different operations. Good agreement has been made with experimental data,which hence validates the implemented physical models and altogether confirms the simulation as a valuable tool for evaluating the characteristics of three-dimensional NAND flash memory.展开更多
In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtua...In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.展开更多
Based on first principle calculations, a comprehensive study of substitutional oxygen defects in hexagonal silicon nitride （β-Si3N4） has been carried out. Firstly, it is found that substitutional oxygen is most lik...Based on first principle calculations, a comprehensive study of substitutional oxygen defects in hexagonal silicon nitride （β-Si3N4） has been carried out. Firstly, it is found that substitutional oxygen is most likely to form clusters at three sites in Si3N4 due to the intense attractive interaction between oxygen defects. Then, by using three analytical tools （trap energy, modified Bader analysis and charge density difference）, we discuss the trap abilities of the three clusters. The result shows that each kind of cluster at the three specific sites presents very different abilities to trap charge carriers （electrons or holes）： two of the three clusters can trap both kinds of charge carriers, confirming their amphoteric property; While the last remaining one is only able to trap hole carriers. Moreover, our studies reveal that the three clusters differ from each other in terms of endurance during the program/erase progress. Taking full account of capturing properties for the three oxygen clusters, including trap ability and endurance, we deem holes rather than electrons to be optimal to act as operational charge carriers for the oxygen defects in Si3N4-based charge trapping memories.展开更多
基金supported by the National Research Foundation of Korea(NRF)grant funded by the government of the Republic of Korea(the Ministry of Science and ICT)(Nos.NRF-2023R1A2C2003247,2021R1C1C2091728,and 2021R1A2C2010695)the Nano&Material Technology Development Program through the National Research Foundation of Korea(NRF)funded by Ministry of Science and ICT(No.RS-2024-00402972)the National Research Council of Science&Technology(NST)grant by the Korea。
文摘The atomically thin nature of two-dimensional(2D)layered materials makes them susceptible to charge trapping by randomly created disorders,adversely affecting carrier dynamics such as charge transport and exciton lifetime.Typically,these disorders lead to poor device performance or require additional space to mitigate performance degradation.In this study,we investigate 2D layered Dion–Jacobson(DJ)-phase oxide perovskite nanosheets,which exhibit charge trapping within their well-defined quantum well(QW)structures,resulting in unique tailoring of electrical conductivity and photoconductivity.These DJ-phase perovskites,composed of tunable atomic constituents,demonstrate resonant tunneling and anomalous charge trapping due to their ultra-clean QWs.Remarkably,the conductivity of insulating HSr_(2)Nb_(3)O_(10)(HSNO)increased over 1000 times upon applying voltage without additional treatments.We observed persistent photoconductivity in 2D vertical heterostructure devices,attributed to charge trapping in QWs,and demonstrated artificial synaptic behaviours in a single flake with tailored energy consumption.Varying the number of perovskite layers significantly allows the tunability of the energy bandgap.This study also highlights the high tunability of 2D perovskite nanosheets,promising various applications,including magnetic,high-k dielectric,and resistive switching devices.Our findings suggest a new class of ionic layered materials with great potential as novel two-dimensional building blocks for device applications.
基金supported partially by the National Basic Research Program of China (Grant No. 2010CB934204)the National Natural Science Foundation of China (Grant No. 60825403)+1 种基金the Director’s Fund of Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS)the National Science and Technology Major Project of China (Grant No. 2009ZX02023-005)
文摘In this paper, we investigate an Al2O3/HfSiO stack as the blocking layer of a metal-oxide-nitride-oxide-silicon- type （MONOS） memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the blocking layer or an Al2O3/HfO2 stack as the blocking layer, the sample with the Al2O3/HfSiO stack as the blocking layer shows high program/erase （P/E） speed and good data retention characteristics. These improved performances can be explained by energy band engineering. The experimental results demonstrate that the memory device with an Al2O3/HfSiO stack as the blocking layer has great potential for further high-performance nonvolatile memory applications.
基金Supported by the National Natural Science Foundation of China under Grant No 616340084the Youth Innovation Promotion Association of Chinese Academy of Sciences under Grant No 2014101+1 种基金the International Cooperation Project of Chinese Academy of Sciencesthe Austrian-Chinese Cooperative R&D Projects under Grant No 172511KYSB20150006
文摘Because of the discrete charge storage mechanism, charge trapping memory（CTM） technique is a good candidate for aerospace and military missions. The total ionization dose（TID） effects on CTM cells with Al2O3/HfO2/Al2O3（AHA） high-k gate stack structure under in-situ 10 keV x-rays are studied. The C-V characteristics at different radiation doses demonstrate that charge stored in the device continues to be leaked away during the irradiation,thereby inducing the shift of flat band voltage（V（fb））. The dc memory window shows insignificant changes, suggesting the existence of good P/E ability. Furthermore, the physical mechanisms of TID induced radiation damages in AHA-based CTM are analyzed.
基金supported by the National Natural Science Foundation of China(Grant No.61106080)the National Science and Technology Major Project of the Ministry of Science and Technology of China(Grant No.2013ZX02305)
文摘Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope(XPS) and transmission electron microscope(TEM)measurements. In addition, Rutherford back scattering(RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer.
基金Project supported by the Key Project of Shanghai Education Committee (Grant No. 08ZZ42)Science and Technology Commission of Shanghai Municipal (Grant Nos. 08PJ14053,08DZ1140702 and 08520511200)
文摘This paper utilizes multilayer organic light-emitting diodes with a thin layer of dye molecules to study the mech- anism of charge trapping under different electric regimes. It demonstrates that the carrier trapping was independent of the current density in devices using fluorescent material as the emitting molecule while this process was exactly opposite when phosphorescent material was used. The triplet-triplet annihilation and dissociation of excitons into free charge carriers was considered to contribute to the decrease in phosphorescent emission under high electric fields. Moreover, the fluorescent dye molecule with a lower energy gap and ionized potential than the host emitter was observed to facilitate the carrier trapping mechanism, and it would produce photon emission.
基金supported by the National Key Research&Development Project of China(Grant No.2022YFA1204100)the National Natural Science Foundation of China(Grant No.62488201)+1 种基金CAS Project for Young Scientists in Basic Research(Grant No.YSBR-003)the Innovation Program of Quantum Science and Technology(Grant No.2021ZD0302700)。
文摘Charge trapping devices incorporating 2D materials and high-κdielectrics have emerged as promising candidates for compact,multifunctional memory devices compatible with silicon-based manufacturing processes.However,traditional charge trapping devices encounter bottlenecks including complex device structure and low operation speed.Here,we demonstrate an ultrafast reconfigurable direct charge trapping device utilizing only a 30 nm-thick Al_(2)O_(3)trapping layer with a MoS_(2)channel,where charge traps reside within the Al_(2)O_(3)bulk confirmed by transfer curves with different gatevoltage sweeping rates and photoluminescence(PL)spectra.The direct charging tapping device shows exceptional memory performance in both three-terminal and two-terminal operation modes characterized by ultrafast three-terminal operation speed(~300 ns),an extremely low OFF current of 10^(-14)A,a high ON/OFF current ratio of up to 10^(7),and stable retention and endurance properties.Furthermore,the device with a simple symmetrical structure exhibits VDpolarity-dependent reverse rectification behavior in the high resistance state(HRS),with a rectification ratio of 10^(5).Additionally,utilizing the synergistic modulation of the conductance of the MoS_(2)channel by V_(D)and V_(G),it achieves gate-tunable reverse rectifier and ternary logic capabilities.
基金Project supported by the National Natural Science Foundation of China(Grant No.92264104)。
文摘We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect,we first establish a model to simulate the electron trapping behavior in n-type Si FeFET.The model is based on the quantum mechanical electron tunneling theory.And then,we use the pulsed I_d-V_g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET.Our model fits the experimental data well.By fitting the model with the experimental data,we get the following conclusions.(i)During the positive operation pulse,electrons in the Si substrate are mainly trapped at the interface between the ferroelectric(FE)layer and interlayer(IL)of the FeFET gate stack by inelastic trap-assisted tunneling.(ii)Based on our model,we can get the number of electrons trapped into the gate stack during the positive operation pulse.(iii)The model can be used to evaluate trap parameters,which will help us to further understand the fatigue mechanism of FeFET.
基金Supported by the National Basic Research Program of China under Grant No 2011CBA00602the National Key Scientific and Technological Project under Grant No 2013ZX01032001-001-003
文摘Impact of band-engineering to the performance of charge trapping memory with HfO2/Ta2O5/HfO2 （HTH） as the charge trapping layer is investigated. Compared with devices with the same total HfO2 thickness, structures with Ta2O5 closer to substrates show larger program/erase window, because the 2nd HfO2 （next to blocking oxide） serving as part of blocking oxide reduces the current tunneling out of/in the charge trapping layer during program and erase. Moreover, trapped charge centroid is modulated and contributed more to the fiat-band voltage shift. Further experiments prove that devices with a thicker 2nd HfO2 layer exhibit larger saturate fiat-band shift in both program and erase operation. The optimized device achieves a 7 V memory window and good reliability characteristics.
基金the National Natural Science Foundation of China(Grant Nos.12105340,12035019,and12075290)the Youth Innovation Promotion Association of the Chinese Academy of Sciences(Grant No.2020412)。
文摘Heavy ion irradiation effects on charge trapping memory(CTM)capacitors with TiN/Al_(2)O_(3)/HfO_(2)/Al_(2)O_(3)/HfO_(2)/SiO_(2)/p-Si structure have been investigated.The ion-induced interface charges and oxide trap charges were calculated and analyzed by capacitance-voltage(C-V)characteristics.The C-V curves shift towards the negative direction after swift heavy ion irradiation,due to the net positive charges accumulating in the trapping layer.The memory window decreases with the increase of ion fluence at high voltage,which results from heavy ion-induced structural damage in the blocking layer.The mechanism of heavy ion irradiation effects on CTM capacitors is discussed in detail with energy band diagrams.The results may help to better understand the physical mechanism of heavy ion-induced degradation of CTM capacitors.
基金Project supported by the National Natural Science Foundation of China (Grant No.61874029)。
文摘Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.
基金supported by Samsung Electronics Co.Ltd and RFDP 20060001050
文摘We have evaluated the effects of recombination processes in a charge storage layer, either between trapped electrons and trapped holes or between trapped carriers and free carriers, on charge trapping memory cell＇s performances by numerical simulation. Recombination is an indispensable mechanism in charge trapping memory. It helps charge convert process between negative and positive charges in the charge storage layer during charge trapping memory programming/erasing operation. It can affect the speed of programming and erasing operations.
基金supported by the National Natural Science Foundation of China(Grant Nos.61404005,61421005,and 91434201)
文摘In this work, the trap-assisted tunneling（TAT） mechanism is modeled as a two-step physical process for charge trapping memory（CTM）. The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.
基金supported by the National Natural Science Foundation of China(Grant Nos.613760966,1327813,61404126 and 11947115)the Natural Science Foundation of Henan Province under(Grant No.202300410444)Foreign Experts Program of Ministry of Science and Technology in China(Grant No.G2021026027L)。
文摘We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO_(2) interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 10^(12) cm^(–2) and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.
基金Project supported by the National Basic Research Program of China (Grant No. 2010CB934203)
文摘We evaluate the influence of the thermally assisted tunneling （TAT） mechanism on charge trapping memory （CTM） cell performance by numerical simulation, and comprehensively analyse the effects of the temperature, trap depth, distribution of trapped charge, gate voltage and parameters of TAT on erasing/programming speed and retention performance. TAT is an indispensable mechanism in CTM that can increase the detrapping probability of trapped charge. Our results reveal that the TAT effect causes the sensitivity of cell performance to temperature and it could affect the operational speed, especially for the erasing operation. The results show that the retention performance degrades compared with when the TAT mechanism is ignored.
基金Supported by the National Science and Technology Major Project of China under Grant No 2013ZX02303007the National Key Research and Development Program of China under Grant No 2016YFA0301701the Youth Innovation Promotion Association of the Chinese Academy of Sciences under Grant No 2016112
文摘We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.
基金supported by the National Natural Science Foundation of China(62288102,51933005,61604081)the National Key R&D Program of China(2024YFB3612600)+1 种基金the Basic Research Program of Jiangsu(BK20240033)the Natural Science Foundation Project of Jilin Province(20230101294JC).
文摘OFET-type optical memories using light bias as the fourth terminal enable low voltage electrical stresses to suffice in generating substantial memory window and photoassisted multibit storage.The undefined molecular structure and trapping mechanism of most storage media limit their practical applications.Herein,we report a series of charge trapping materials with the rigid and planar conjugated structure of benzo[1,2-b:4,5-b’]dithiophene(BDT)acting as the charge trapping site and photoresponsive group,while the insulated(triisopropylsilyl)acetylene(TIPS)unit is introduced to prevent the leakage path of the charge.The pentacene-based OFET memory with solution-processing TTIPS-BDT shows fast trapping speed,tunable ambipolar memory,large memory window and reliable charge retention,which is obviously improved compare to the performance of BDT and DTIPS-BDT devices.In addition,the charge trapping,memory characteristics and photoresponsive behaviors are also discussed in detail.The TTIPS-BDT device shows a specific response to green light illumination.This study suggests that BDT derivatives serving as charge trapping elements possess potential applications in future photoresponsive memory and plastic electronics.
基金supported by the MOST (Grant Nos. 2010CB934200,2011CBA00600)the National Natural Science Foundation of China (Grant Nos. 60825403,61176073)+1 种基金the Director's Fund of IMECASthe National Science and Technology Major Project of China (Grant No.2009ZX02023-005)
文摘We have investigated the effect of post deposition annealing (PDA) temperature of Al2O3 blocking layer on the performance of charge trapping memory capacitors. Two splits of PDA were performed in N2 ambient at 850°C/60 s and 1050°C/60 s, respectively. The 1050°C annealed capacitor could be programmed and erased normally by using Fowler-Nordheim (FN) injection. In contrast, the 850°C annealed device could not be erased, even though it could be programmed properly. By measuring the gate leakage current and the flatband voltage shift, we found the erase failure in the 850°C annealed device was due to a larger gate back-injection leakage current at Vg<0. The trend of gate leakage current was further verified in two Al/Al2O3/SiO2/p-Si control capacitors with the same PDA splits. In addition, constant voltage stress measurements on control capacitors in the FN regime showed that the change of gate leakage current followed an empirical Curie-von Schweidler law at Vg<0. The data pointed out the importance to further study the relation between PDA conditions and the defect generation properties in Al2O3 blocking layer.
基金supported by National Natural Science Foundation of China (Grant No. 91230107)National Basic Research Program of China (973) (Grant No. 2013CBA01604)National High Technology Research and Development Program of China (863) (Grant No. 2015AA016501)
文摘This work presents a self-consistent two-dimensional(2-D) simulation method with unified physical models for different operation regimes of charge trapping memory. The simulation carefully takes into consideration the tunneling process, charge trapping/de-trapping mechanisms, and 2-D drift-diffusion transport within the storage layer. A string of three memory cells has been simulated and evaluated for different gate stack compositions and temperatures. The simulator is able to describe the charge transport behavior along bitline and tunneling directions under different operations. Good agreement has been made with experimental data,which hence validates the implemented physical models and altogether confirms the simulation as a valuable tool for evaluating the characteristics of three-dimensional NAND flash memory.
基金Project supported by the National Basic Research Program of China(No.2006CB302700)
文摘In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.
基金supported by the National Youth Science Foundation of China(No.61006064)
文摘Based on first principle calculations, a comprehensive study of substitutional oxygen defects in hexagonal silicon nitride （β-Si3N4） has been carried out. Firstly, it is found that substitutional oxygen is most likely to form clusters at three sites in Si3N4 due to the intense attractive interaction between oxygen defects. Then, by using three analytical tools （trap energy, modified Bader analysis and charge density difference）, we discuss the trap abilities of the three clusters. The result shows that each kind of cluster at the three specific sites presents very different abilities to trap charge carriers （electrons or holes）： two of the three clusters can trap both kinds of charge carriers, confirming their amphoteric property; While the last remaining one is only able to trap hole carriers. Moreover, our studies reveal that the three clusters differ from each other in terms of endurance during the program/erase progress. Taking full account of capturing properties for the three oxygen clusters, including trap ability and endurance, we deem holes rather than electrons to be optimal to act as operational charge carriers for the oxygen defects in Si3N4-based charge trapping memories.
