Aim To discuss the basic CORDIC algorithm that can be applied to digital signal processing and its applying condition called convergence range.Methods In addition to the original basic equation, another group iterativ...Aim To discuss the basic CORDIC algorithm that can be applied to digital signal processing and its applying condition called convergence range.Methods In addition to the original basic equation, another group iterative equation was used to evaluate the correspondent values of input data that did not lie within the convergence range. Results and Conclusion The improved CORDIC algorithm removes the limits of the range of convergence and can adapt itself to the variations of input values. The correctness of improved CORDIC algorithms has been proved by calculating examples.展开更多
To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorit...To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.展开更多
The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass ...The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.展开更多
相位细分技术是提高精密仪器测量分辨率和精度的关键技术。传统的机械、光学等细分技术已难以满足当前高精度测量领域的需求。基于坐标旋转数字计算(Coordinate Rotation Digital Computer,CORDIC)方法的角度计算原理,将输入的正交信号...相位细分技术是提高精密仪器测量分辨率和精度的关键技术。传统的机械、光学等细分技术已难以满足当前高精度测量领域的需求。基于坐标旋转数字计算(Coordinate Rotation Digital Computer,CORDIC)方法的角度计算原理,将输入的正交信号转换为向量(x,y),通过多次旋转迭代使向量最终收敛于X轴,对旋转角度进行求和即可得到目标角度值。基于FPGA用Verilog语言编写CORDIC算法,可以实现相位细分、信号辨向和整周期计数功能,通过扩展数据位宽消除了算法迭代过程中产生的舍入误差。对改进算法进行了仿真与实验验证,结果表明经过20级迭代后其理论分辨率为0.4″,计算角度的误差为±0.5″,光栅测角系统实际测量误差减小了约98.42%。该算法通过对正交信号进行精密细分来计算精密仪器的相角变化量,在工程应用中具有普适性。展开更多
CORDIC(coordinate rotation digital computing)算法能够通过简单的移位、加减运算得到任意输入角度的正弦或余弦值,具有速度快、精度灵活可调、硬件实现简单等优点。在深入分析CORDIC基本算法原理的基础上,实现了一种改进算法,这种改...CORDIC(coordinate rotation digital computing)算法能够通过简单的移位、加减运算得到任意输入角度的正弦或余弦值,具有速度快、精度灵活可调、硬件实现简单等优点。在深入分析CORDIC基本算法原理的基础上,实现了一种改进算法,这种改进算法的迭代方向由输入角二进制表示时的各位位值直接确定,避免了CORDIC基本算法中迭代方向需由剩余角度计算结果决定的不足,从而提高了CORDIC算法的运行速度,减小了电路规模,并且对算法的综合性能也有一定改善。展开更多
针对基于FPGA的分布式导航系统中涉及大量的三角函数运算,而传统的查找表或差值法计算,在精度、运算速度方面不能兼得,且占用资源多,文中提出了基于CORDIC算法的反正切函数计算的改进方法与流水线结构的实现方法,使用VHDL硬件描述语言...针对基于FPGA的分布式导航系统中涉及大量的三角函数运算,而传统的查找表或差值法计算,在精度、运算速度方面不能兼得,且占用资源多,文中提出了基于CORDIC算法的反正切函数计算的改进方法与流水线结构的实现方法,使用VHDL硬件描述语言进行编程实现,在Quartus II 9.0中对算法进行功能仿真,最后通过Altera公司的FPGA Cyclone II系列芯片进行了具体验证。验证结果表明,针对累加器中因截尾而产生的误差所作的算法改进,显著地提高了算法精度,而且运算速度快。展开更多
文摘Aim To discuss the basic CORDIC algorithm that can be applied to digital signal processing and its applying condition called convergence range.Methods In addition to the original basic equation, another group iterative equation was used to evaluate the correspondent values of input data that did not lie within the convergence range. Results and Conclusion The improved CORDIC algorithm removes the limits of the range of convergence and can adapt itself to the variations of input values. The correctness of improved CORDIC algorithms has been proved by calculating examples.
基金The National High Technology Research and Development Program of China (863 Program)(No.2007AA01Z280)
文摘To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.
文摘The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.
文摘相位细分技术是提高精密仪器测量分辨率和精度的关键技术。传统的机械、光学等细分技术已难以满足当前高精度测量领域的需求。基于坐标旋转数字计算(Coordinate Rotation Digital Computer,CORDIC)方法的角度计算原理,将输入的正交信号转换为向量(x,y),通过多次旋转迭代使向量最终收敛于X轴,对旋转角度进行求和即可得到目标角度值。基于FPGA用Verilog语言编写CORDIC算法,可以实现相位细分、信号辨向和整周期计数功能,通过扩展数据位宽消除了算法迭代过程中产生的舍入误差。对改进算法进行了仿真与实验验证,结果表明经过20级迭代后其理论分辨率为0.4″,计算角度的误差为±0.5″,光栅测角系统实际测量误差减小了约98.42%。该算法通过对正交信号进行精密细分来计算精密仪器的相角变化量,在工程应用中具有普适性。
文摘CORDIC(coordinate rotation digital computing)算法能够通过简单的移位、加减运算得到任意输入角度的正弦或余弦值,具有速度快、精度灵活可调、硬件实现简单等优点。在深入分析CORDIC基本算法原理的基础上,实现了一种改进算法,这种改进算法的迭代方向由输入角二进制表示时的各位位值直接确定,避免了CORDIC基本算法中迭代方向需由剩余角度计算结果决定的不足,从而提高了CORDIC算法的运行速度,减小了电路规模,并且对算法的综合性能也有一定改善。
文摘针对基于FPGA的分布式导航系统中涉及大量的三角函数运算,而传统的查找表或差值法计算,在精度、运算速度方面不能兼得,且占用资源多,文中提出了基于CORDIC算法的反正切函数计算的改进方法与流水线结构的实现方法,使用VHDL硬件描述语言进行编程实现,在Quartus II 9.0中对算法进行功能仿真,最后通过Altera公司的FPGA Cyclone II系列芯片进行了具体验证。验证结果表明,针对累加器中因截尾而产生的误差所作的算法改进,显著地提高了算法精度,而且运算速度快。
