A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two t...A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two tables are provided to make it obvious to understand for the characteristics of spurious tones changing with related parameters.Some suggestions are given for the design of a DLL based RF CMOS oscillators.展开更多
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ...By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.展开更多
The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main...The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main driver to satisfy slew rate of output data, receiver includes optimized topology to improve preci- sion of received data. The circuit simulation is based on Cadence’s spectre software and Taiwan Semiconduc- tor Manufacture Corporation’s library of 0.25μm mixed-signal Complementary Metal-Oxide Semiconductor (CMOS) model. The front and post-simulation results reveal that the transceiver designed can transmit and re- ceive high-speed data in 480Mbps, which is in agreement with USB2.0 specification. The chip of physi- cal-layer transceiver has been designed and implemented with 0.25μm standard CMOS technology.展开更多
Metamaterial devices(metadevices)have been developed in progress aiming to generate extraordinary performance over traditional de-vices in the(sub-)terahertz(THz)domain,and their planar integra-tion with complementary...Metamaterial devices(metadevices)have been developed in progress aiming to generate extraordinary performance over traditional de-vices in the(sub-)terahertz(THz)domain,and their planar integra-tion with complementary-metal-oxide-semiconductor(CMOS)cir-cuits pave a new way to build miniature silicon plasmonics that over-comes existing challenges in chip-to-chip communication.In an effort towards low-power,crosstalk-tolerance,and high-speed data link for future exascale data centers,this article reviews the recent progress on two metamaterials,namely,the spoof surface plasmon polaritons(SPPs),and the split-ring resonator(SRR),as well as their imple-mentations in silicon,focusing primarily on their fundamental the-ories,design methods,and implementations for future THz commu-nications.Owing to their respective dispersion characteristic at THz,these two metadevices are highly expected to play an important role in miniature integrated circuits and systems toward compact size,dense integration,and outstanding performance.A design example of a fully integrated sub-THz CMOS silicon plasmonic system integrating these two metadevices is provided to demonstrate a dual-channel crosstalk-tolerance and energy-efficient on-off keying(OOK)communication system.Future directions and potential applications for THz metade-vices are discussed.展开更多
文摘A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two tables are provided to make it obvious to understand for the characteristics of spurious tones changing with related parameters.Some suggestions are given for the design of a DLL based RF CMOS oscillators.
文摘By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.
文摘The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main driver to satisfy slew rate of output data, receiver includes optimized topology to improve preci- sion of received data. The circuit simulation is based on Cadence’s spectre software and Taiwan Semiconduc- tor Manufacture Corporation’s library of 0.25μm mixed-signal Complementary Metal-Oxide Semiconductor (CMOS) model. The front and post-simulation results reveal that the transceiver designed can transmit and re- ceive high-speed data in 480Mbps, which is in agreement with USB2.0 specification. The chip of physi- cal-layer transceiver has been designed and implemented with 0.25μm standard CMOS technology.
基金supported by National Natural Science Founda-tion of China(NSFC)(Key Program Grant No.62034007)the Key-Area Research and Development Program of Guangdong Province(Grant No.2019B010116002)+3 种基金Guangdong Basic and Applied Basic Research Founda-tion(Grant 2019B1515120024)Shenzhen Science and Technology Program(Grant No.KQTD20200820113051096)supported by Na-tional Natural Science Foundation of China under Grant 62101122Natural Science Foundation of Jiangsu Province under Grant BK20210212.
文摘Metamaterial devices(metadevices)have been developed in progress aiming to generate extraordinary performance over traditional de-vices in the(sub-)terahertz(THz)domain,and their planar integra-tion with complementary-metal-oxide-semiconductor(CMOS)cir-cuits pave a new way to build miniature silicon plasmonics that over-comes existing challenges in chip-to-chip communication.In an effort towards low-power,crosstalk-tolerance,and high-speed data link for future exascale data centers,this article reviews the recent progress on two metamaterials,namely,the spoof surface plasmon polaritons(SPPs),and the split-ring resonator(SRR),as well as their imple-mentations in silicon,focusing primarily on their fundamental the-ories,design methods,and implementations for future THz commu-nications.Owing to their respective dispersion characteristic at THz,these two metadevices are highly expected to play an important role in miniature integrated circuits and systems toward compact size,dense integration,and outstanding performance.A design example of a fully integrated sub-THz CMOS silicon plasmonic system integrating these two metadevices is provided to demonstrate a dual-channel crosstalk-tolerance and energy-efficient on-off keying(OOK)communication system.Future directions and potential applications for THz metade-vices are discussed.
