The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. ...The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.展开更多
基金This research is partially supported by the DARPA Advanced Microelectronics Program, SRC Front EndProcess Project, and NSF. This paper contains a review of UTB and FinFET research published by D. Hisamoto, Y-K. Choi, X. Huang, W-C. Lee, C. Kuo, L. Chan
文摘The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.
