The deceleration of Moore's law and the energy–latency drawbacks of the von Neumann bottleneck have heightened the pursuit for beyond-CMOS designs that integrate memory and compute.Self-rectifying memristors(SRMs...The deceleration of Moore's law and the energy–latency drawbacks of the von Neumann bottleneck have heightened the pursuit for beyond-CMOS designs that integrate memory and compute.Self-rectifying memristors(SRMs)have emerged as promising building blocks for high-performance,low-power systems by combining resistive switching with intrinsic diode-like behavior.Their unidirectional conduction inhibits sneak-path currents in crossbar arrays devoid of external selectors,while nonlinear I–V characteristics,adjustable conductance states,low operating voltages,and rapid switching facilitate efficient vector–matrix operations,neuromorphic plasticity,and hardware security primitives.This review synthesizes the working mechanisms of SRMs,surveys material,and structural strategies and compares device metrics relevant to array-scale deployment(rectification ratio,nonlinearity,endurance,retention,variability,and operating voltage).We assess SRM-enabled in-memory computing and neuromorphic applications,as well as security functions such as physical unclonable functions and reconfigurable cryptographic primitives.Integration pathways toward CMOS compatibility are analyzed,including back-end-of-line thermal budgets,uniformity,write disturb mitigation,and reliability.Finally,we outline key challenges and opportunities:materials/architecture co-design,precision analog training,stochasticity control/exploitation,3D stacking,and standardized benchmarking that can accelerate large-scale SRM adoption.Through the use of specialized materials and structural optimization,SRMs are set to provide selector-free,densely integrated,and energy-efficient hardware for future information processing.展开更多
系统级电路辐照效应的复杂性对建模方法提出了高精度与高速度的双重要求。CMOS(互补金属氧化物半导体)工艺收发器作为系统级电路的核心常用器件,其总剂量效应的精准建模仿真至关重要。为此,本文提出一种适用于CMOS收发器的总剂量效应行...系统级电路辐照效应的复杂性对建模方法提出了高精度与高速度的双重要求。CMOS(互补金属氧化物半导体)工艺收发器作为系统级电路的核心常用器件,其总剂量效应的精准建模仿真至关重要。为此,本文提出一种适用于CMOS收发器的总剂量效应行为级仿真方法:采用输入输出缓冲区信息规范(input/output buffer information specification,IBIS)模型表征Hi-1573器件的缓冲区特性,通过VHDL-AMS语言完成器件功能区的精细化建模。为验证方法有效性,开展了^(60)Co伽马射线辐照实验,基于实验数据优化总剂量效应模块参数,将其与IBIS总剂量效应模型融合进行仿真。结果显示,仿真结果与实验数据的性能退化趋势高度吻合,充分证明了该行为级仿真方法在CMOS收发器总剂量效应建模中的可行性与可靠性。展开更多
针对智能导钻传感系统在极端温度条件下的应用需求,基于国内0.15μm SOI CMOS工艺,采用正负温度系数电阻平衡、MOS晶体管背栅反馈以及偏置电流温度补偿等技术,设计一款可工作于-50~250℃的宽温区低温漂基准电压源。仿真结果表明,该基准...针对智能导钻传感系统在极端温度条件下的应用需求,基于国内0.15μm SOI CMOS工艺,采用正负温度系数电阻平衡、MOS晶体管背栅反馈以及偏置电流温度补偿等技术,设计一款可工作于-50~250℃的宽温区低温漂基准电压源。仿真结果表明,该基准电压源在-50~250℃温度范围内能够稳定输出2.537 V的基准电压,温度系数为14.45 ppm/℃时,低频下电源抑制比达到-63.1 dB,在不同电源电压和工艺角下仿真均表现出良好的稳定性。该电路适用于需要在宽温度区域内保持高精度和稳定性的电子系统。展开更多
In this study,the mechanism and characteristics of the responseαparticles and the damage caused by them in CMOS active pixel(APS)sensors were investigated.A detection and compensation algorithm for dead pixels caused...In this study,the mechanism and characteristics of the responseαparticles and the damage caused by them in CMOS active pixel(APS)sensors were investigated.A detection and compensation algorithm for dead pixels caused byαparticle ionizing radiation was proposed,and the effects of dead-pixel compensation algorithms were compared and analyzed under different parameter conditions.The experimental results show thatαparticle response signal has highest accuracy at 9 dB gain,with an obvious“target-ring”distribution.With increasing cumulative dose,the CMOS APS pedestal tends to saturation while dead pixels continue increasing.Though some pixel damage recovers through natural annealing,the dead-to-noise ratio increases with irradiation time,reaching 32.54%after 72 h.A hierarchical clustering dead-pixel detection method is proposed,categorizing pixels into two types:those within and outside the response event.A classification compensation strategy combining mean and majority filtering is proposed.This compensation algorithm can address dead-pixel interference without affectingαparticle radiation response data.When iterated multiple times and with integration time exceeding 6.31 ms,the number of dead pixels can be effectively reduced.展开更多
To address the challenges of complexity,power consumption,and cost constraints in traditional display driver integrated circuits(DDICs)caused by external NOR Flash and SRAM,this work proposes an embedded resistive ran...To address the challenges of complexity,power consumption,and cost constraints in traditional display driver integrated circuits(DDICs)caused by external NOR Flash and SRAM,this work proposes an embedded resistive random-access memory(RRAM)integration solution based on a 40 nm high-voltage CMOS logic platform.Targeting the yield fluctuations and stability challenges during RRAM mass production,systematic process optimizations are implemented to achieve synergistic improvements in RRAM performance and yield.Through modifications to the film sputtering and pre-deposition treatment,the withinwafer resistance uniformity(RSU)of the oxygen-deficient layer(ODL)thin film is improved from 11%to 8%,while inter-wafer process stability variation reduces from 23%to below 6%.Consequently,the yield of 8 Mb RRAM embedded mass production products increases from 87%to 98.5%.In terms of device performance,the RRAM demonstrates a fast 4.8 ns read speed,exceptional read disturb immunity of 3×10^(8) cycles at 95℃,10^(3) write/erase endurance cycles for the 1 Mb cells,and data retention of 12.5 years at 125℃.Post high-temperature operating life(HTOL)testing exhibits stable high/low resistance window.This study provides process optimization strategies and a reliability assurance framework for the mass production of highly integrated,low-power embedded RRAM display driver IC.展开更多
基于高速低功耗混合应用场景下对互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)比较器性能的综合需求,系统研究其结构优化设计。阐述动态比较器在响应速度、功耗控制、输入失调与噪声抑制等方面的关键技术,介绍...基于高速低功耗混合应用场景下对互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)比较器性能的综合需求,系统研究其结构优化设计。阐述动态比较器在响应速度、功耗控制、输入失调与噪声抑制等方面的关键技术,介绍前置放大器、电源控制、闭环反馈及偏置电路的协同优化策略。结合65 nm CMOS工艺下的仿真测试结果,分析主要性能指标在典型工况下的表现,验证所提结构的可实现性与工程适应性。结果表明,该设计能够在低功耗约束下保持高速响应。展开更多
基金supported by the National Natural Science Foundation of China(Grants No.92364204 and 62204219)the open research fund of Suzhou Laboratory(Grants No.SZLAB-1208-2024-TS012)+1 种基金Major Program of Natural Science Foundation of Zhejiang Province(Grants No.LDT23F0401)Zhejiang Province Introduces and Cultivates Leading Innovation and Entrepreneurship Teams(Grants No.2023R01011)。
文摘The deceleration of Moore's law and the energy–latency drawbacks of the von Neumann bottleneck have heightened the pursuit for beyond-CMOS designs that integrate memory and compute.Self-rectifying memristors(SRMs)have emerged as promising building blocks for high-performance,low-power systems by combining resistive switching with intrinsic diode-like behavior.Their unidirectional conduction inhibits sneak-path currents in crossbar arrays devoid of external selectors,while nonlinear I–V characteristics,adjustable conductance states,low operating voltages,and rapid switching facilitate efficient vector–matrix operations,neuromorphic plasticity,and hardware security primitives.This review synthesizes the working mechanisms of SRMs,surveys material,and structural strategies and compares device metrics relevant to array-scale deployment(rectification ratio,nonlinearity,endurance,retention,variability,and operating voltage).We assess SRM-enabled in-memory computing and neuromorphic applications,as well as security functions such as physical unclonable functions and reconfigurable cryptographic primitives.Integration pathways toward CMOS compatibility are analyzed,including back-end-of-line thermal budgets,uniformity,write disturb mitigation,and reliability.Finally,we outline key challenges and opportunities:materials/architecture co-design,precision analog training,stochasticity control/exploitation,3D stacking,and standardized benchmarking that can accelerate large-scale SRM adoption.Through the use of specialized materials and structural optimization,SRMs are set to provide selector-free,densely integrated,and energy-efficient hardware for future information processing.
文摘系统级电路辐照效应的复杂性对建模方法提出了高精度与高速度的双重要求。CMOS(互补金属氧化物半导体)工艺收发器作为系统级电路的核心常用器件,其总剂量效应的精准建模仿真至关重要。为此,本文提出一种适用于CMOS收发器的总剂量效应行为级仿真方法:采用输入输出缓冲区信息规范(input/output buffer information specification,IBIS)模型表征Hi-1573器件的缓冲区特性,通过VHDL-AMS语言完成器件功能区的精细化建模。为验证方法有效性,开展了^(60)Co伽马射线辐照实验,基于实验数据优化总剂量效应模块参数,将其与IBIS总剂量效应模型融合进行仿真。结果显示,仿真结果与实验数据的性能退化趋势高度吻合,充分证明了该行为级仿真方法在CMOS收发器总剂量效应建模中的可行性与可靠性。
基金supported by the National Natural Science Foundation of China(No.11905102)Hunan Provincial Postgraduate Research and Innovation Project(No.QL20230234)。
文摘In this study,the mechanism and characteristics of the responseαparticles and the damage caused by them in CMOS active pixel(APS)sensors were investigated.A detection and compensation algorithm for dead pixels caused byαparticle ionizing radiation was proposed,and the effects of dead-pixel compensation algorithms were compared and analyzed under different parameter conditions.The experimental results show thatαparticle response signal has highest accuracy at 9 dB gain,with an obvious“target-ring”distribution.With increasing cumulative dose,the CMOS APS pedestal tends to saturation while dead pixels continue increasing.Though some pixel damage recovers through natural annealing,the dead-to-noise ratio increases with irradiation time,reaching 32.54%after 72 h.A hierarchical clustering dead-pixel detection method is proposed,categorizing pixels into two types:those within and outside the response event.A classification compensation strategy combining mean and majority filtering is proposed.This compensation algorithm can address dead-pixel interference without affectingαparticle radiation response data.When iterated multiple times and with integration time exceeding 6.31 ms,the number of dead pixels can be effectively reduced.
文摘To address the challenges of complexity,power consumption,and cost constraints in traditional display driver integrated circuits(DDICs)caused by external NOR Flash and SRAM,this work proposes an embedded resistive random-access memory(RRAM)integration solution based on a 40 nm high-voltage CMOS logic platform.Targeting the yield fluctuations and stability challenges during RRAM mass production,systematic process optimizations are implemented to achieve synergistic improvements in RRAM performance and yield.Through modifications to the film sputtering and pre-deposition treatment,the withinwafer resistance uniformity(RSU)of the oxygen-deficient layer(ODL)thin film is improved from 11%to 8%,while inter-wafer process stability variation reduces from 23%to below 6%.Consequently,the yield of 8 Mb RRAM embedded mass production products increases from 87%to 98.5%.In terms of device performance,the RRAM demonstrates a fast 4.8 ns read speed,exceptional read disturb immunity of 3×10^(8) cycles at 95℃,10^(3) write/erase endurance cycles for the 1 Mb cells,and data retention of 12.5 years at 125℃.Post high-temperature operating life(HTOL)testing exhibits stable high/low resistance window.This study provides process optimization strategies and a reliability assurance framework for the mass production of highly integrated,low-power embedded RRAM display driver IC.
