利用压缩感知和预留子载波技术,提出一种改进的余弦调制滤波器组多载波通信系统的时域脉冲干扰抑制方法。不同于传统采用滤波器组多载波(filter bank multi-carrier,FBMC)脉冲干扰抑制方法:该方案可以在已知时域脉冲干扰数目的情况下,...利用压缩感知和预留子载波技术,提出一种改进的余弦调制滤波器组多载波通信系统的时域脉冲干扰抑制方法。不同于传统采用滤波器组多载波(filter bank multi-carrier,FBMC)脉冲干扰抑制方法:该方案可以在已知时域脉冲干扰数目的情况下,对其位置与大小精确估计。接收端首先通过预留子载波上的信息进行脉冲干扰的预判,然后利用压缩感知贪婪基追踪算法估计出其他载波上的混合干扰,最后结合预判信息,在混合干扰中提取出纯净的脉冲干扰并予以消除。仿真实验对上述方法与传统干扰抑制方法进行了可靠性比较,在信噪比达到15 d B时,随着信噪比的提高,提出的干扰抑制方法能够更加有效地抑制时域脉冲干扰,极大地降低了系统的误符号率。展开更多
This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications ...This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications of the OTA are derived from the requirements of ADC. Simulation shows that for a lpF load capacitance, this OTA achieves a high DC gain （approximately 145dB） and a wide unity-gain bandwidth （above 750MHz） at a phase margin 58°. In a configuration where the closed loop-gain is 4,the design spends about 18ns for settling with 0.05% accuracy. Simulations of this design are performed in SMIC CMOS 0.18μm technology.展开更多
文摘利用压缩感知和预留子载波技术,提出一种改进的余弦调制滤波器组多载波通信系统的时域脉冲干扰抑制方法。不同于传统采用滤波器组多载波(filter bank multi-carrier,FBMC)脉冲干扰抑制方法:该方案可以在已知时域脉冲干扰数目的情况下,对其位置与大小精确估计。接收端首先通过预留子载波上的信息进行脉冲干扰的预判,然后利用压缩感知贪婪基追踪算法估计出其他载波上的混合干扰,最后结合预判信息,在混合干扰中提取出纯净的脉冲干扰并予以消除。仿真实验对上述方法与传统干扰抑制方法进行了可靠性比较,在信噪比达到15 d B时,随着信噪比的提高,提出的干扰抑制方法能够更加有效地抑制时域脉冲干扰,极大地降低了系统的误符号率。
文摘This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications of the OTA are derived from the requirements of ADC. Simulation shows that for a lpF load capacitance, this OTA achieves a high DC gain （approximately 145dB） and a wide unity-gain bandwidth （above 750MHz） at a phase margin 58°. In a configuration where the closed loop-gain is 4,the design spends about 18ns for settling with 0.05% accuracy. Simulations of this design are performed in SMIC CMOS 0.18μm technology.
