The growth of computing power in data centers(DCs)leads to an increase in energy consumption and noise pollution of air cooling systems.Chip-level cooling with high-efficiency coolant is one of the promising methods t...The growth of computing power in data centers(DCs)leads to an increase in energy consumption and noise pollution of air cooling systems.Chip-level cooling with high-efficiency coolant is one of the promising methods to address the cooling challenge for high-power devices in DCs.Hybrid nanofluid(HNF)has the advantages of high thermal conductivity and good rheological properties.This study summarizes the numerical investigations of HNFs in mini/micro heat sinks,including the numerical methods,hydrothermal characteristics,and enhanced heat transfer technologies.The innovations of this paper include:(1)the characteristics,applicable conditions,and scenarios of each theoretical method and numerical method are clarified;(2)the molecular dynamics(MD)simulation can reveal the synergy effect,micro motion,and agglomeration morphology of different nanoparticles.Machine learning(ML)presents a feasiblemethod for parameter prediction,which provides the opportunity for the intelligent regulation of the thermal performance of HNFs;(3)the HNFs flowboiling and the synergy of passive and active technologies may further improve the overall efficiency of liquid cooling systems in DCs.This review provides valuable insights and references for exploring the multi-phase flow and heat transport mechanisms of HNFs,and promoting the practical application of HNFs in chip-level liquid cooling in DCs.展开更多
A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-co...A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-code interference. A fractional sample equalizer is also derived to further improve the performance of the receiver. Performance analysis and the calculation of the output signal to interference ratio (SINR) at each receiver antenna are presented to help direct the design of equalization weight in a more optimal manner. System simulations demonstrate the significant performance gain over conventional Rake receiver and high potential of MIMO HSDPA for high-data-rate packet transmission.展开更多
This work is focused on the structure design of MMSE linear equalizers in the downlink of CDMA-based multi-user communication systems. Previous work was mostly focused on the performance comparison between ZF and MMSE...This work is focused on the structure design of MMSE linear equalizers in the downlink of CDMA-based multi-user communication systems. Previous work was mostly focused on the performance comparison between ZF and MMSE linear equalizers and the conclusion is that the performance based on MMSE criterion is much better than that based on ZF one. In this paper, we only discuss MMSE equalizer and a new block structure of MMSE linear equalizer is derived from the traditional structure of this kind of equalizer. Furthermore, a block MMSE linear equalizer is improved through using the overlap-save technique. Simulation results shaw that the average performance of improved block MMSE linear equalizers is better than those of the block MMSE equalizers and traditional MMSE equalizers. At the same time, the computation complexity of all these MMSE equalizers is given. It is shown that the comple：rity of proposed block MMSE equalizers is lower than that of the traditional equalizers with optimal delay, D, when the length of the filter in traditional MMSE equalizers equals the block size of block MMSE equalizers.展开更多
Enhancing the vibration resistance of micro-electro-mechanical systems(MEMS)resonators in complex environments is a critical issue that urgently needs to be addressed.This paper presents a chip-scale locally resonant ...Enhancing the vibration resistance of micro-electro-mechanical systems(MEMS)resonators in complex environments is a critical issue that urgently needs to be addressed.This paper presents a chip-scale locally resonant phononic crystal(LRPnC)plate based on a folded helical beam structure.Through finite element simulation and theoretical analysis,the bandgap characteristics and vibration suppression mechanisms of this structure were thoroughly investigated.The results show that the structure exhibits a complete bandgap in the frequency range of 9.867-14.605 kHz,and the bandgap can be effectively tuned by adjusting the structural parameters.Based on this,the influence of the number of unit cell layers on the vibration reduction performance was further studied,and a finite periodic LRPnC plate was constructed.Numerical studies have shown that the LRPnC plate can achieve more than-30 dB of vibration attenuation within the bandgap and effectively suppress y-direction coupling vibrations caused by x-direction propagating waves.In addition,its chip-scale size and planar structure design provide new ideas and methods for the engineering application of phononic crystal technology in the field of MEMS vibration isolation.展开更多
为降低核安全级数字化控制系统(Digital Control System,DCS)关键芯片在工作过程中的温升,提高系统的可靠性,本研究提出利用机器学习方法对核安全级DCS关键芯片进行布局优化。首先,试验测得DCS在事故工况(环境温度55℃)下的芯片稳态温度...为降低核安全级数字化控制系统(Digital Control System,DCS)关键芯片在工作过程中的温升,提高系统的可靠性,本研究提出利用机器学习方法对核安全级DCS关键芯片进行布局优化。首先,试验测得DCS在事故工况(环境温度55℃)下的芯片稳态温度,随后结合有限元分析计算模拟试验过程。基于有限元模型生成100组随机芯片排布下的中央处理器(Central Processing Unit,CPU)和可编程逻辑门阵列(Field Programmable Gate Array,FPGA)稳态温度数据,利用多输出支持向量回归(Multi-output Support Vector Regression,M-SVR)算法建立温度预测模型,结合粒子群优化(Particle Swarm Optimization,PSO)算法计算出温升最小的芯片位置坐标。进一步,利用有限元分析验证该优化位置坐标下的芯片稳态温度。研究结果表明,有限元模型能较好反映试验现象,SVR-PSO算法优化得到的芯片布局使CPU和FPGA的稳态温度分别降低2.4℃和2.5℃。因此,本研究提出的算法能够实现芯片布局优化,有效降低其工作温升,提升核安全级DCS系统可靠性。展开更多
为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理...为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理、任务自动映射、通讯任务乱序执行等机制。实验结果表明,该动态调度协处理器不仅能够实现任务级乱序执行等基本设计目标,还具有极低的调度开销,相较于基于动态记分牌算法的调度器,运行多个子孔径距离压缩算法的时间降低达17.13%。研究结果证明文章设计的动态调度协处理器能够有效优化目标场景下的任务调度效果。展开更多
随着神经网络模型日益复杂,片上网络(Network on Chip,NoC)在异构计算系统中扮演着关键通信角色。然而,传统NoC仿真工具普遍缺乏对矩阵处理单元与RISC V可编程核等异构计算单元的支持,难以满足大规模人工智能任务对实时性、吞吐量与能...随着神经网络模型日益复杂,片上网络(Network on Chip,NoC)在异构计算系统中扮演着关键通信角色。然而,传统NoC仿真工具普遍缺乏对矩阵处理单元与RISC V可编程核等异构计算单元的支持,难以满足大规模人工智能任务对实时性、吞吐量与能效的需求。为应对上述挑战,提出并实现了一种面向异构计算的行为级NoC仿真框架,具备高精度节点建模、动态流水线机制、混合任务感知路由算法以及全链路可视化调试能力。实验结果表明,本文框架在平均延迟、吞吐量与可视化调试效率方面相较传统方法均显著提升,尤其在混合任务流和硬件故障场景下展现出更高的稳定性与可扩展性,为下一代智能计算平台的NoC设计与优化提供了重要支撑。展开更多
为了降低传感器的驱动电压,提高该器件的品质因数和信噪比,该文研究封装材料和工艺对真空封装性能的影响,针对一种微机电系统(MEMS)谐振式微型电场敏感结构芯片,采用独特的共晶键合技术,实现该传感器的芯片级真空封装。实验结果表明,该...为了降低传感器的驱动电压,提高该器件的品质因数和信噪比,该文研究封装材料和工艺对真空封装性能的影响,针对一种微机电系统(MEMS)谐振式微型电场敏感结构芯片,采用独特的共晶键合技术,实现该传感器的芯片级真空封装。实验结果表明,该传感器封装后的品质因数达到了30727.4,是常压封装的500倍;该封装器件具有更低的驱动电压,只需要直流分量100 m V和交流分量60 m Vp-p,与常压测试时相比,分别只有原来的1/200和1/16。展开更多
基金funded by the Science and Technology Project of Tianjin(No.24YDTPJC00680)the National Natural Science Foundation of China(No.52406191).
文摘The growth of computing power in data centers(DCs)leads to an increase in energy consumption and noise pollution of air cooling systems.Chip-level cooling with high-efficiency coolant is one of the promising methods to address the cooling challenge for high-power devices in DCs.Hybrid nanofluid(HNF)has the advantages of high thermal conductivity and good rheological properties.This study summarizes the numerical investigations of HNFs in mini/micro heat sinks,including the numerical methods,hydrothermal characteristics,and enhanced heat transfer technologies.The innovations of this paper include:(1)the characteristics,applicable conditions,and scenarios of each theoretical method and numerical method are clarified;(2)the molecular dynamics(MD)simulation can reveal the synergy effect,micro motion,and agglomeration morphology of different nanoparticles.Machine learning(ML)presents a feasiblemethod for parameter prediction,which provides the opportunity for the intelligent regulation of the thermal performance of HNFs;(3)the HNFs flowboiling and the synergy of passive and active technologies may further improve the overall efficiency of liquid cooling systems in DCs.This review provides valuable insights and references for exploring the multi-phase flow and heat transport mechanisms of HNFs,and promoting the practical application of HNFs in chip-level liquid cooling in DCs.
文摘A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-code interference. A fractional sample equalizer is also derived to further improve the performance of the receiver. Performance analysis and the calculation of the output signal to interference ratio (SINR) at each receiver antenna are presented to help direct the design of equalization weight in a more optimal manner. System simulations demonstrate the significant performance gain over conventional Rake receiver and high potential of MIMO HSDPA for high-data-rate packet transmission.
文摘This work is focused on the structure design of MMSE linear equalizers in the downlink of CDMA-based multi-user communication systems. Previous work was mostly focused on the performance comparison between ZF and MMSE linear equalizers and the conclusion is that the performance based on MMSE criterion is much better than that based on ZF one. In this paper, we only discuss MMSE equalizer and a new block structure of MMSE linear equalizer is derived from the traditional structure of this kind of equalizer. Furthermore, a block MMSE linear equalizer is improved through using the overlap-save technique. Simulation results shaw that the average performance of improved block MMSE linear equalizers is better than those of the block MMSE equalizers and traditional MMSE equalizers. At the same time, the computation complexity of all these MMSE equalizers is given. It is shown that the comple：rity of proposed block MMSE equalizers is lower than that of the traditional equalizers with optimal delay, D, when the length of the filter in traditional MMSE equalizers equals the block size of block MMSE equalizers.
基金supported by National Natural Science Foundation of China(No.62271262).
文摘Enhancing the vibration resistance of micro-electro-mechanical systems(MEMS)resonators in complex environments is a critical issue that urgently needs to be addressed.This paper presents a chip-scale locally resonant phononic crystal(LRPnC)plate based on a folded helical beam structure.Through finite element simulation and theoretical analysis,the bandgap characteristics and vibration suppression mechanisms of this structure were thoroughly investigated.The results show that the structure exhibits a complete bandgap in the frequency range of 9.867-14.605 kHz,and the bandgap can be effectively tuned by adjusting the structural parameters.Based on this,the influence of the number of unit cell layers on the vibration reduction performance was further studied,and a finite periodic LRPnC plate was constructed.Numerical studies have shown that the LRPnC plate can achieve more than-30 dB of vibration attenuation within the bandgap and effectively suppress y-direction coupling vibrations caused by x-direction propagating waves.In addition,its chip-scale size and planar structure design provide new ideas and methods for the engineering application of phononic crystal technology in the field of MEMS vibration isolation.
文摘为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理、任务自动映射、通讯任务乱序执行等机制。实验结果表明,该动态调度协处理器不仅能够实现任务级乱序执行等基本设计目标,还具有极低的调度开销,相较于基于动态记分牌算法的调度器,运行多个子孔径距离压缩算法的时间降低达17.13%。研究结果证明文章设计的动态调度协处理器能够有效优化目标场景下的任务调度效果。
文摘随着神经网络模型日益复杂,片上网络(Network on Chip,NoC)在异构计算系统中扮演着关键通信角色。然而,传统NoC仿真工具普遍缺乏对矩阵处理单元与RISC V可编程核等异构计算单元的支持,难以满足大规模人工智能任务对实时性、吞吐量与能效的需求。为应对上述挑战,提出并实现了一种面向异构计算的行为级NoC仿真框架,具备高精度节点建模、动态流水线机制、混合任务感知路由算法以及全链路可视化调试能力。实验结果表明,本文框架在平均延迟、吞吐量与可视化调试效率方面相较传统方法均显著提升,尤其在混合任务流和硬件故障场景下展现出更高的稳定性与可扩展性,为下一代智能计算平台的NoC设计与优化提供了重要支撑。
文摘为了降低传感器的驱动电压,提高该器件的品质因数和信噪比,该文研究封装材料和工艺对真空封装性能的影响,针对一种微机电系统(MEMS)谐振式微型电场敏感结构芯片,采用独特的共晶键合技术,实现该传感器的芯片级真空封装。实验结果表明,该传感器封装后的品质因数达到了30727.4,是常压封装的500倍;该封装器件具有更低的驱动电压,只需要直流分量100 m V和交流分量60 m Vp-p,与常压测试时相比,分别只有原来的1/200和1/16。
