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一种VNPN双极器件总电离剂量辐射加固方法
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作者 葛超洋 谢儒彬 +4 位作者 李燕妃 鞠镇毅 彭洪 丁兵 常瑞恒 《微电子学》 2025年第5期868-875,共8页
针对标准0.18μm BCD(Bipolar-CMOS-DMOS)工艺中的VNPN(Vertical NPN)双极器件,分析了总电离剂量辐射(TID)加固的重点区域。提出了一种新颖的VNPN双极器件总电离剂量辐射加固方法,利用薄氧化层和多晶硅双层结构取代基射结上方的浅沟槽隔... 针对标准0.18μm BCD(Bipolar-CMOS-DMOS)工艺中的VNPN(Vertical NPN)双极器件,分析了总电离剂量辐射(TID)加固的重点区域。提出了一种新颖的VNPN双极器件总电离剂量辐射加固方法,利用薄氧化层和多晶硅双层结构取代基射结上方的浅沟槽隔离(STI)结构。由于薄氧化层厚度远小于STI氧化层厚度,在相同总电离剂量辐射下,薄氧化层产生的氧化层固定电荷和界面态的数量大大减少,显著加强了VNPN双极器件的抗总电离剂量辐射能力。选取了3种典型VNPN双极器件,进行了总电离剂量辐射实验。实验结果表明,采用该加固方法的3种VNPN双极器件在1500 Gy(Si)总电离剂量辐射后,归一化电流增益均能保持在0.900左右,验证了薄氧化层和多晶硅双层结构加固方法的有效性。对3种加固的VNPN双极器件进行了本征基区尺寸偏差实验,研究了本征基区尺寸对总电离剂量辐射后归一化电流增益的影响。实验结果表明,在相同总电离剂量辐射下,本征基区尺寸越小,归一化电流增益越大。因此,使用薄氧化层和多晶硅双层结构是一种有效的VNPN双极器件总电离剂量辐射加固方法。另外,缩小本征基区尺寸能够进一步降低VNPN双极器件在总电离剂量辐射前后归一化电流增益的变化幅度,从而确保器件在总电离剂量辐射后的性能与总电离剂量辐射前的初始值基本一致。 展开更多
关键词 双极器件 总电离剂量(TID)辐射 0.18μm BCD(bipolar-cmos-dmos)工艺
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Review of Technologies for High-Voltage Integrated Circuits 被引量:1
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作者 Bo Zhang Wentong Zhang +3 位作者 Le Zhu Jian Zu Ming Qiao Zhaoji Li 《Tsinghua Science and Technology》 SCIE EI CAS CSCD 2022年第3期495-511,共17页
High-Voltage power Integrated Circuits(HVICs) are widely used to realize high-efficiency power conversions(e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS(BCD... High-Voltage power Integrated Circuits(HVICs) are widely used to realize high-efficiency power conversions(e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS(BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage(HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance,and process compatibility with low-voltage circuits. The REduced SURFace field(RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field(ENDIF) and REduced BULk Field(REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors’ group,such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed. 展开更多
关键词 High-Voltage ICs(HVICs) high-voltage integrated technology bipolar-cmos-dmos(BCD)process integrated power semiconductor devices SUPERJUNCTION
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