System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to opti...System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.展开更多
Low-power designs are getting increased significance in numerous applications like high-performance computing and wireless communication due to the rise in power dissipation.Power dissipation of VLSI(very large scale ...Low-power designs are getting increased significance in numerous applications like high-performance computing and wireless communication due to the rise in power dissipation.Power dissipation of VLSI(very large scale integration)circuits in test mode is much higher than in the normal operation mode due to the high frequency of applied test patterns.Product lifetime,yield,reduced performance,and circuit damage will result from this additional power consumption in testing.Therefore,the main objective of today’s test applications is to minimize power dissipation by increasing the correlation of applied successive test vectors.Low-power test pattern generator(TPG)using LFSR(linear feedback shift register)and binary to the excess-4 converter and binary ripple counter is proposed.The test vectors generated by the TPG have a high correlation between successive test vectors,which leads to minimum switching.During the testing of benchmark circuits,the proposed method shows a significant reduction in dynamic power consumption concerning its peer works.展开更多
文摘System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.
文摘Low-power designs are getting increased significance in numerous applications like high-performance computing and wireless communication due to the rise in power dissipation.Power dissipation of VLSI(very large scale integration)circuits in test mode is much higher than in the normal operation mode due to the high frequency of applied test patterns.Product lifetime,yield,reduced performance,and circuit damage will result from this additional power consumption in testing.Therefore,the main objective of today’s test applications is to minimize power dissipation by increasing the correlation of applied successive test vectors.Low-power test pattern generator(TPG)using LFSR(linear feedback shift register)and binary to the excess-4 converter and binary ripple counter is proposed.The test vectors generated by the TPG have a high correlation between successive test vectors,which leads to minimum switching.During the testing of benchmark circuits,the proposed method shows a significant reduction in dynamic power consumption concerning its peer works.
