The product of the cutoff frequency and breakdown voltage （fT x BVCEo） is an important figure of merit （FOM） to characterize overall performance of heterojunction bipolar transistor （HBT）. In this paper, an appr...The product of the cutoff frequency and breakdown voltage （fT x BVCEo） is an important figure of merit （FOM） to characterize overall performance of heterojunction bipolar transistor （HBT）. In this paper, an approach to introducing a thin N＋-buried layer into N collector region in silicon-on-insulator （SOI） SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional （2D） numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOl structure, the effects of SOI insulation layer thickness （TBox） on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fw, slightly increases BVcEO to some extent, but ultimately degrades the FOM of fTXBVcEo. Although the fT, BVcEo, and the FOM of fTXBVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiOa layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N＋-buried layer is introduced into collector region to not only improve the FOM of fT ×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N＋-buried layer in collector region is investigated in detail. The result show that the FOM of fT xBVcEo is improved and the device temperature decreases as the N＋-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N＋-buried layer into collector region provides an effective method to improve SOI SiGe HBT overall performance.展开更多
Compared with BVcEo, BVcEs is more related to collector optimization and more practical significance, so that BVcEs × fT rather than BVcEo ×fT is employed in representing the limit of the product of the brea...Compared with BVcEo, BVcEs is more related to collector optimization and more practical significance, so that BVcEs × fT rather than BVcEo ×fT is employed in representing the limit of the product of the breakdown voltage-cutoff frequency in SiGe HBT for collector engineering design. Instead of a single decrease in collector doping to improve BVcEs × fT and BVcEo × fT, a novel thin composite of N- and P＋ doping layers inside the CB SCR is presented to improve the well-known tradeoff between the breakdown voltage and cut-off frequency in SiGe HBT, and BVCES and BVCEO are improved respectively with slight degradation in fTAs a result, the BVcEs × fT product is improved from 537.57 to 556.4 GHz.V, and the BVcEo ×fT product is improved from 309.51 to 326.35 GHz.V.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61574010,60776051,61006059,and 61006044)the Beijing Municipal Natural Science Foundation,China(Grant No.4142007)the Beijing Municipal Education Committee,China(Grant No.KM200910005001)
文摘The product of the cutoff frequency and breakdown voltage （fT x BVCEo） is an important figure of merit （FOM） to characterize overall performance of heterojunction bipolar transistor （HBT）. In this paper, an approach to introducing a thin N＋-buried layer into N collector region in silicon-on-insulator （SOI） SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional （2D） numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOl structure, the effects of SOI insulation layer thickness （TBox） on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fw, slightly increases BVcEO to some extent, but ultimately degrades the FOM of fTXBVcEo. Although the fT, BVcEo, and the FOM of fTXBVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiOa layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N＋-buried layer is introduced into collector region to not only improve the FOM of fT ×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N＋-buried layer in collector region is investigated in detail. The result show that the FOM of fT xBVcEo is improved and the device temperature decreases as the N＋-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N＋-buried layer into collector region provides an effective method to improve SOI SiGe HBT overall performance.
基金supported by the National Natural Science Foundation of China(Nos.60776051,61006059,61006044)the Beijing Natural Science Foundation(Nos.4082007,4143059,4142007,4122014)the Beijing Municipal Education Committee(Nos.KM200710005015,KM200910005001)
文摘Compared with BVcEo, BVcEs is more related to collector optimization and more practical significance, so that BVcEs × fT rather than BVcEo ×fT is employed in representing the limit of the product of the breakdown voltage-cutoff frequency in SiGe HBT for collector engineering design. Instead of a single decrease in collector doping to improve BVcEs × fT and BVcEo × fT, a novel thin composite of N- and P＋ doping layers inside the CB SCR is presented to improve the well-known tradeoff between the breakdown voltage and cut-off frequency in SiGe HBT, and BVCES and BVCEO are improved respectively with slight degradation in fTAs a result, the BVcEs × fT product is improved from 537.57 to 556.4 GHz.V, and the BVcEo ×fT product is improved from 309.51 to 326.35 GHz.V.
