研究了光电探测器(PD)的结构、性能以及后续放大电路,实现了塑料光纤通信的高速单片集成光接收芯片。首先,根据工艺流程和参数,采用器件模拟软件对PD结构进行了建模,并对其光谱响应度和结电容进行了理论推导及仿真。基于Cadence/spectr...研究了光电探测器(PD)的结构、性能以及后续放大电路,实现了塑料光纤通信的高速单片集成光接收芯片。首先,根据工艺流程和参数,采用器件模拟软件对PD结构进行了建模,并对其光谱响应度和结电容进行了理论推导及仿真。基于Cadence/spectre软件和仿真得到的PD参数对由跨阻放大器、限幅放大器和输出缓冲电路组成的后续放大电路进行了协同设计。采用0.5μm BCD(Bipolar,CMOS and DMOS)工艺对单个PD以及PD和后续放大电路单片集成电路进行了流片、封装和测试。结果表明:PD的光谱响应曲线的峰值波长和仿真结果较一致,约为700nm,PD结构更适合短波长探测;PD的结电容随着反向电压的增大而减小,结电容越大,光接收芯片的带宽越小;对于650nm的入射光,在小于10-9的误码率条件下,光接收机的灵敏度为-14dBm;最后得到了150Mb/s速率的清晰眼图。实验结果显示,设计的高速单片集成光接收机可以应用于百兆速率光纤入户通信系统。展开更多
A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9...A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.展开更多
文摘研究了光电探测器(PD)的结构、性能以及后续放大电路,实现了塑料光纤通信的高速单片集成光接收芯片。首先,根据工艺流程和参数,采用器件模拟软件对PD结构进行了建模,并对其光谱响应度和结电容进行了理论推导及仿真。基于Cadence/spectre软件和仿真得到的PD参数对由跨阻放大器、限幅放大器和输出缓冲电路组成的后续放大电路进行了协同设计。采用0.5μm BCD(Bipolar,CMOS and DMOS)工艺对单个PD以及PD和后续放大电路单片集成电路进行了流片、封装和测试。结果表明:PD的光谱响应曲线的峰值波长和仿真结果较一致,约为700nm,PD结构更适合短波长探测;PD的结电容随着反向电压的增大而减小,结电容越大,光接收芯片的带宽越小;对于650nm的入射光,在小于10-9的误码率条件下,光接收机的灵敏度为-14dBm;最后得到了150Mb/s速率的清晰眼图。实验结果显示,设计的高速单片集成光接收机可以应用于百兆速率光纤入户通信系统。
文摘A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.
