基于双边市场的三个客观现象,即(1)平台维系用户的成本不同导致了不同类型用户对平台的利润贡献率不同;(2)BBPD 是双边平台普遍采用的一种定价策略;(3)用户在同一双边平台进行多次交易,本文构建了一个完全垄断双边平台的两期动态博弈模...基于双边市场的三个客观现象,即(1)平台维系用户的成本不同导致了不同类型用户对平台的利润贡献率不同;(2)BBPD 是双边平台普遍采用的一种定价策略;(3)用户在同一双边平台进行多次交易,本文构建了一个完全垄断双边平台的两期动态博弈模型,通过分析运营成本对用户进入价格、市场份额、平台利润的影响,研究双边平台不同运营成本用户的管理问题,并分析用户成本差异化对平台定价策略的影响。研究发现:仅HPC-B,CC-B,HPC-N和CC-N情况下平台第一期利润与高低成本系数呈现 U 型关系;当成本差异化程度较小时,CC-B,HPC-N和CC-N情形下平台第一期利润与高低成本系数呈现单调递增。展开更多
This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector...This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector（BBPFD） with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm;. Measured results show that the BBPLL operates at a frequency range from0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1μs @ 100 MHz frequency jump.The figure-of-merit of the fast-locking BBPLL is-334 dB.展开更多
文摘基于双边市场的三个客观现象,即(1)平台维系用户的成本不同导致了不同类型用户对平台的利润贡献率不同;(2)BBPD 是双边平台普遍采用的一种定价策略;(3)用户在同一双边平台进行多次交易,本文构建了一个完全垄断双边平台的两期动态博弈模型,通过分析运营成本对用户进入价格、市场份额、平台利润的影响,研究双边平台不同运营成本用户的管理问题,并分析用户成本差异化对平台定价策略的影响。研究发现:仅HPC-B,CC-B,HPC-N和CC-N情况下平台第一期利润与高低成本系数呈现 U 型关系;当成本差异化程度较小时,CC-B,HPC-N和CC-N情形下平台第一期利润与高低成本系数呈现单调递增。
基金Project supported by the National Nature Science Foundation of China(Nos.61331003,61474108)the National Key Technology Research and Development Program of the Ministry of Science and Technology of China(No.2016ZX03001002)
文摘This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector（BBPFD） with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm;. Measured results show that the BBPLL operates at a frequency range from0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1μs @ 100 MHz frequency jump.The figure-of-merit of the fast-locking BBPLL is-334 dB.
