Owing to its large aperture and advanced receivers,research plans for the Qitai 110 m radio telescope(QTT)include a variety of spectral line scientific studies.Sequential construction of receiver systems and multidisc...Owing to its large aperture and advanced receivers,research plans for the Qitai 110 m radio telescope(QTT)include a variety of spectral line scientific studies.Sequential construction of receiver systems and multidisciplinary planning require overcoming serious challenges to spectral line digital backend development,notably to digitize,process,and transmit considerable quantities of observational data,to minimize time-to-science with an easily scalable architecture,and to provide robust,high-quality data.As a proof-of-concept for the QTT backend,here we implement a baseband spectral line digital backend with a SNAP+GPU architecture.The SNAP-based digital frontend comprises two digitization links(1000 MHz,8-bit),two parallel quad-channel preprocessing modules,a quantization module,and a finite-state packaging module,generating a 100-MHz bandwidth digital link from the original analog signal through high-speed Ethernet transmission.The GPU node receives preprocessed baseband packets,constructs a ring buffer for lossless unpacking and distributing,with real-time data reception and caching,and conducts real-time spectral analysis(frequency resolution:3.051 kHz)of the 100 MHz baseband data.We evaluated system performance experimentally using spectral line observations with the Nanshan 26-m radio telescope(NSRT).For the QTT,the SNAP digital frontend will be seamlessly migrated to a radio frequency system-on-chip(RFSoC)architecture,resulting in five-and tenfold increases in instantaneous bandwidth and data throughput,respectively.The low-coupling digital frontend and GPU node can be easily extended to multiple nodes.展开更多
Baseband design and implementation for micro/pico base stations （mBS） in 5G ultra-dense network （UDN） is studied. Low cost is an essential requirement for mBS baseband in UDN. Digital baseband cost of ASIC/ASIP （...Baseband design and implementation for micro/pico base stations （mBS） in 5G ultra-dense network （UDN） is studied. Low cost is an essential requirement for mBS baseband in UDN. Digital baseband cost of ASIC/ASIP （Application Specific Integrated Circuit / Instruction-set processor） is of the most uncertainty in roBS system. However. the actual costs and hardware feasibility of the baseband are yet unknown to network deployers and researchers. In this paper, we studied the baseband hardware system design and implementation for low-cost roBS. We analyzed popular baseband algorithms and architectures for both full-digital and hybrid beamforming （BF） for UDN. We then proposed feasible chip-level solutions for the baseband with up to 128-antenna BS system, and estimated their implementation cost. Results show that among lull-digital BF algorithms, zero-forcing is a choice of high performance and low cost; for hybrid BF, 4×32 architecture （32 RF chains） provides good reduction in baseband cost with acceptable performance loss, thus it can be a preferable solution under low cost consider- ation. The proposed system planning method can also be used for the design of other related systems.展开更多
This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three ...This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three coprocessors that are used for synchronization, FFT and channel decoder. In this MIMO OFDM system, the Zero Correlation Zone （ZCZ） code is used as the synchronization word preamble of packet in the physical layer in order to avoid the interference from other transmitting antennas. Furthermore, a simple channel estimation algorithm is proposed which is appropriate tbr the SIMD DSP computation.展开更多
Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of ...Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of areduced data rate. In order to achieve a higher overall systemperformance, a novel adaptive transceiver architecture whichflexibly combines both UCD and UCD ＋ STBC technologies isproposed. The channel state information （CSI） feedback pathwas added to the precoder to select which coding method wasto be used, i.e. UCD alone or UCD ＋ STBC. With thesmaller constellation sizes, Matlab simulation results showthat, the adaptive transceiver architecture will select the UCD-only mode under the higher SNR conditions in order to achievea higher bit rate. The UCD ＋ STBC mode will be selectedunder the lower SNR conditions （e. g., SNR 〈 10 dB） inorder to maintain good BER performance at the cost of areduced data rate. This architecture was implemented andverified using both UMC 0.18 ASIC process technology and aXilinx xc4vlx Virtex-4 FPGA at 150 MHz. The simulationresults demonstrate that the required number of reconfigurablearithmetic unit slices grows linearly with the channel matrixsize, while the number of adder array unit and reconfigurablelogic unit slices increases slightly with the constellation size.展开更多
Baseband ASIP designs for handsets are discussed based on the author's R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performan...Baseband ASIP designs for handsets are discussed based on the author's R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performance with power consumption in mind. A SDR ASIP baseband system architecture is proposed for 4G and 3G mobile handsets. Function partitions for heterogeneous symbol processors are introduced to get higher performance over cost. Three structures for DFE, FFE, and Matrix symbol ASIP are proposed. The concept of bit parallel processor is introduced. Challenges of baseband processors for UDN of 5G were briefly introduced. Conclusions on ASIP architecture and system design are given for different baseband processors on different products.展开更多
The Chaotic Baseband Wireless Communication System(CBWCS)is expected to eliminate the Inter-Symbol Interference(ISI)caused by multipath propagation by using the optimal decoding threshold that is the sum of the ISI ca...The Chaotic Baseband Wireless Communication System(CBWCS)is expected to eliminate the Inter-Symbol Interference(ISI)caused by multipath propagation by using the optimal decoding threshold that is the sum of the ISI caused by past decoded bits and the ISI caused by future transmitting bits.However,the current technique is only capable of removing partial effects of the ISI,because only past decoded bits are available for the suboptimal decoding threshold calculation.The unavailability of the future information needed for the optimal decoding threshold is an obstacle to further improve the Bit Error Rate(BER)performance.In contrast to the previous method using Echo State Network(ESN)to predict one future bit,the proposed method in this paper predicts the optimal decoding threshold directly using ESN.The proposed ESN-based threshold prediction method simplifies the symbol decoding operation by avoiding the iterative prediction of the output waveform points using ESN and accumulated error caused by the iterative operation.With this approach,the calculation complexity is reduced compared to the previous ESN-based approach.The proposed method achieves better BER performance compared to the previous method.The reason for this superior result is twofold.First,the proposed ESN is capable of using more future symbols information conveyed by the ESN input to obtain more accurate threshold rather than the previous method in which only one future symbol was available.Second,the proposed method here does not need to estimate the channel information using Least Squared(LS)method,which avoids the extra error caused by inaccurate channel information estimation.Simulation results and experiment based on a wireless open-access research platform under a practical wireless channel show the effectiveness and superiority of the proposed method.展开更多
This paper aims to discuss how to effectively suppress intersymbol interference by optimizing the filter design, so as to achieve a distortion-free output effect, and effectively compensate the transmission characteri...This paper aims to discuss how to effectively suppress intersymbol interference by optimizing the filter design, so as to achieve a distortion-free output effect, and effectively compensate the transmission characteristics of the baseband transmission system in a non-ideal channel environment, so as to minimize the impact of intersymbol crosser. The simulation experiment model of digital optimal baseband transmission and the overall structure of the system are designed based on the Matlab simulation platform, and the parameters of each module in the simulation experiment model are set. The working process and performance of the digital optimal baseband transmission system are simulated, and the conditions and performance of the digital optimal baseband transmission system are verified according to the simulation results.展开更多
The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power...The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.展开更多
In recent years,as China has finished the updating of the fourth generation of network,for guaranteeing the information security of the state,communication chip with complete independent intellectual property right mu...In recent years,as China has finished the updating of the fourth generation of network,for guaranteeing the information security of the state,communication chip with complete independent intellectual property right must be possessed to support the advancement of such project.TD-LTE Baseband Chip is a super-large-scale integrated circuit designed basing on SOC,which needs to carry out coding,etc to the transmitted baseband signal,or carry out decoding,etc to the received baseband signal.LPDDR2 SDRAM is used in the chip design process due to its low power dissipation,high capacity and high reliability.As PHY in the controller architecture of LPDDR2 SDRAM adopts hard core design,it cannot be achieved in Virtex-7 2000T prototype verification platform.This design mainly builds on such prototype verification platform to propose the verification scheme of LPDDR2 SDRAM controller in TD_LTE baseband chip,so as to guarantee that prototype verification in FPGA can be carried out by TD_LTE baseband system,and meanwhile high capacity storage space can be provided to the system.展开更多
This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital bro...This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital broadcasting system（DBS） standards,including DVB-S,DVB-S2,and ABS-S.The cut-off frequency of the baseband circuit can be changed continuously from 4.5 to 32 MHz.The gain adjustment range is from 6 to 55.5 dB with 0.5 dB step.The calibration includes automatic frequency tuning（AFT） and automatic DC offset calibration （DCOC） to achieve less than 6%cut-off frequency deviation and 3 mV residual output offset.The out-of-band IIP2 and IIP3 of the overall chain are 45 dBm and 18 dBm respectively,while the input referred noise（IRN） is 17.4 nV/√Hz.All circuit blocks are operated at 2.8 V from LDO and consume current of 20.4 mA in the receiving mode.展开更多
This paper presents the design and implementation of a low power wide tuning range baseband filter with an accurate on-chip tuning circuit for reconfigurable multistandard wireless transceivers. The realized low pass ...This paper presents the design and implementation of a low power wide tuning range baseband filter with an accurate on-chip tuning circuit for reconfigurable multistandard wireless transceivers. The realized low pass filter （LPF） is a six-order Butterworth type by cascading three stage active-Gm-RC biquadratic cells. A mod- ified linearization technique is used to improve the filter linearity performance at low power consumption. A new process-independent transconductor matching circuit and a new frequency tuning circuit with frequency compen- sation are proposed to achieve a high precision filter frequency response. The proposed LPF is realized in a 130 nm standard CMOS technology. The measured results show that the LPF exhibits a high bandwidth programmability from 0.1 to 25 MHz with a tuning frequency error less than 2.68% over the wide tuning range. The power consump- tion is scalable, ranging from 0.52 to 5.25 mA, from a 1.2 V power supply while achieving a 26.3 dBm in-band IIP3.展开更多
An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. ...An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18/zm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 × 2.6 mm^2 area and consumes 83 mW under typical work modes.展开更多
A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth in 0.35μm CMOS is presented. The circuit consists of two variable gain amplifiers（VGA） in cascade and a Gm-C elliptic low-pass filter（LPF）. Th...A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth in 0.35μm CMOS is presented. The circuit consists of two variable gain amplifiers（VGA） in cascade and a Gm-C elliptic low-pass filter（LPF）. The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption,the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application.Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN,8.9 mW for WCDMA and only 6.5 mW for Bluetooth,all with a 3 V power supply.The analog baseband circuit could provide -10 to ＋40 dB variable gain,third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth,fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN,respectively.展开更多
This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunabili...This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm;and 0.48×0.25 mm;areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）;according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.展开更多
This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibrat...This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.展开更多
A dual-mode analog baseband with digital-assisted DC-offset calibration （DCOC） for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC- offset compo...A dual-mode analog baseband with digital-assisted DC-offset calibration （DCOC） for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC- offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm^2.展开更多
This paper describes a low-pass reconfigurable baseband filter for GSM, TD-SCDMA and WCDMA multi-mode transmitters. To comply with 3GPP emission mask and limit TX leakage at the RX band, the out- of-band noise perform...This paper describes a low-pass reconfigurable baseband filter for GSM, TD-SCDMA and WCDMA multi-mode transmitters. To comply with 3GPP emission mask and limit TX leakage at the RX band, the out- of-band noise performance is optimized. Due to the distortion caused by the subthreshold leakage current of the switches used in capacitor array, a capacitor bypass technique is proposed to improve the filter＇s linearity. An automatic frequency tuning circuit is adopted to compensate the cut-off frequency variation. Simulation results show that the filter achieves an in-band input-referred third-order intercept point （IIP3） of 47 dBm at 1.2-V power supply and the out-of-band noise can meet TX SAW-less requirement for WCDMA ＆ TD-SCDMA. The baseband filter incorporates -40 to 0 dB programmable gain control that is accurately variable in 0.5 dB steps. The filter＇s cut-off frequency can be reconfigured for GSM/TD-SCDMA/WCDMA multi-mode transmitter. The implemented baseband filter draws 3.6 mA from a 1.2-V supply in a 0.13 μm CMOS process.展开更多
基金supported by the “Light in China’s Western Region” program (2022-XBQNXZ012)by the National Natural Science Foundation of China(12073067)
文摘Owing to its large aperture and advanced receivers,research plans for the Qitai 110 m radio telescope(QTT)include a variety of spectral line scientific studies.Sequential construction of receiver systems and multidisciplinary planning require overcoming serious challenges to spectral line digital backend development,notably to digitize,process,and transmit considerable quantities of observational data,to minimize time-to-science with an easily scalable architecture,and to provide robust,high-quality data.As a proof-of-concept for the QTT backend,here we implement a baseband spectral line digital backend with a SNAP+GPU architecture.The SNAP-based digital frontend comprises two digitization links(1000 MHz,8-bit),two parallel quad-channel preprocessing modules,a quantization module,and a finite-state packaging module,generating a 100-MHz bandwidth digital link from the original analog signal through high-speed Ethernet transmission.The GPU node receives preprocessed baseband packets,constructs a ring buffer for lossless unpacking and distributing,with real-time data reception and caching,and conducts real-time spectral analysis(frequency resolution:3.051 kHz)of the 100 MHz baseband data.We evaluated system performance experimentally using spectral line observations with the Nanshan 26-m radio telescope(NSRT).For the QTT,the SNAP digital frontend will be seamlessly migrated to a radio frequency system-on-chip(RFSoC)architecture,resulting in five-and tenfold increases in instantaneous bandwidth and data throughput,respectively.The low-coupling digital frontend and GPU node can be easily extended to multiple nodes.
基金supporting from National High Technical Research and Development Program of China(863 program)2014AA01A705 is sincerely acknowledged by authors
文摘Baseband design and implementation for micro/pico base stations （mBS） in 5G ultra-dense network （UDN） is studied. Low cost is an essential requirement for mBS baseband in UDN. Digital baseband cost of ASIC/ASIP （Application Specific Integrated Circuit / Instruction-set processor） is of the most uncertainty in roBS system. However. the actual costs and hardware feasibility of the baseband are yet unknown to network deployers and researchers. In this paper, we studied the baseband hardware system design and implementation for low-cost roBS. We analyzed popular baseband algorithms and architectures for both full-digital and hybrid beamforming （BF） for UDN. We then proposed feasible chip-level solutions for the baseband with up to 128-antenna BS system, and estimated their implementation cost. Results show that among lull-digital BF algorithms, zero-forcing is a choice of high performance and low cost; for hybrid BF, 4×32 architecture （32 RF chains） provides good reduction in baseband cost with acceptable performance loss, thus it can be a preferable solution under low cost consider- ation. The proposed system planning method can also be used for the design of other related systems.
基金Supported by the National Natural Science Foundation of China (No.60476013).
文摘This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three coprocessors that are used for synchronization, FFT and channel decoder. In this MIMO OFDM system, the Zero Correlation Zone （ZCZ） code is used as the synchronization word preamble of packet in the physical layer in order to avoid the interference from other transmitting antennas. Furthermore, a simple channel estimation algorithm is proposed which is appropriate tbr the SIMD DSP computation.
基金The National Natural Science Foundation of China(No.61376025)the Industry-Academic Joint Technological Innovations FundP roject of Jiangsu(No.BY2013003-11)the Scientific Innovation Research of College Graduates in Jiangsu Province(No.KYLX_0273)
文摘Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of areduced data rate. In order to achieve a higher overall systemperformance, a novel adaptive transceiver architecture whichflexibly combines both UCD and UCD ＋ STBC technologies isproposed. The channel state information （CSI） feedback pathwas added to the precoder to select which coding method wasto be used, i.e. UCD alone or UCD ＋ STBC. With thesmaller constellation sizes, Matlab simulation results showthat, the adaptive transceiver architecture will select the UCD-only mode under the higher SNR conditions in order to achievea higher bit rate. The UCD ＋ STBC mode will be selectedunder the lower SNR conditions （e. g., SNR 〈 10 dB） inorder to maintain good BER performance at the cost of areduced data rate. This architecture was implemented andverified using both UMC 0.18 ASIC process technology and aXilinx xc4vlx Virtex-4 FPGA at 150 MHz. The simulationresults demonstrate that the required number of reconfigurablearithmetic unit slices grows linearly with the channel matrixsize, while the number of adder array unit and reconfigurablelogic unit slices increases slightly with the constellation size.
基金supported by the National HighTech Research and Development Program of China (863 Program) 2014AA01A705.
文摘Baseband ASIP designs for handsets are discussed based on the author's R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performance with power consumption in mind. A SDR ASIP baseband system architecture is proposed for 4G and 3G mobile handsets. Function partitions for heterogeneous symbol processors are introduced to get higher performance over cost. Three structures for DFE, FFE, and Matrix symbol ASIP are proposed. The concept of bit parallel processor is introduced. Challenges of baseband processors for UDN of 5G were briefly introduced. Conclusions on ASIP architecture and system design are given for different baseband processors on different products.
文摘The Chaotic Baseband Wireless Communication System(CBWCS)is expected to eliminate the Inter-Symbol Interference(ISI)caused by multipath propagation by using the optimal decoding threshold that is the sum of the ISI caused by past decoded bits and the ISI caused by future transmitting bits.However,the current technique is only capable of removing partial effects of the ISI,because only past decoded bits are available for the suboptimal decoding threshold calculation.The unavailability of the future information needed for the optimal decoding threshold is an obstacle to further improve the Bit Error Rate(BER)performance.In contrast to the previous method using Echo State Network(ESN)to predict one future bit,the proposed method in this paper predicts the optimal decoding threshold directly using ESN.The proposed ESN-based threshold prediction method simplifies the symbol decoding operation by avoiding the iterative prediction of the output waveform points using ESN and accumulated error caused by the iterative operation.With this approach,the calculation complexity is reduced compared to the previous ESN-based approach.The proposed method achieves better BER performance compared to the previous method.The reason for this superior result is twofold.First,the proposed ESN is capable of using more future symbols information conveyed by the ESN input to obtain more accurate threshold rather than the previous method in which only one future symbol was available.Second,the proposed method here does not need to estimate the channel information using Least Squared(LS)method,which avoids the extra error caused by inaccurate channel information estimation.Simulation results and experiment based on a wireless open-access research platform under a practical wireless channel show the effectiveness and superiority of the proposed method.
文摘This paper aims to discuss how to effectively suppress intersymbol interference by optimizing the filter design, so as to achieve a distortion-free output effect, and effectively compensate the transmission characteristics of the baseband transmission system in a non-ideal channel environment, so as to minimize the impact of intersymbol crosser. The simulation experiment model of digital optimal baseband transmission and the overall structure of the system are designed based on the Matlab simulation platform, and the parameters of each module in the simulation experiment model are set. The working process and performance of the digital optimal baseband transmission system are simulated, and the conditions and performance of the digital optimal baseband transmission system are verified according to the simulation results.
基金supported in part by the National Natural Science Foundation of China(No.61306027)
文摘The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.
基金National Science and Technology Major Project of Ministry of Industry and Information Technology in 2011(2011ZX03003-003-02)
文摘In recent years,as China has finished the updating of the fourth generation of network,for guaranteeing the information security of the state,communication chip with complete independent intellectual property right must be possessed to support the advancement of such project.TD-LTE Baseband Chip is a super-large-scale integrated circuit designed basing on SOC,which needs to carry out coding,etc to the transmitted baseband signal,or carry out decoding,etc to the received baseband signal.LPDDR2 SDRAM is used in the chip design process due to its low power dissipation,high capacity and high reliability.As PHY in the controller architecture of LPDDR2 SDRAM adopts hard core design,it cannot be achieved in Virtex-7 2000T prototype verification platform.This design mainly builds on such prototype verification platform to propose the verification scheme of LPDDR2 SDRAM controller in TD_LTE baseband chip,so as to guarantee that prototype verification in FPGA can be carried out by TD_LTE baseband system,and meanwhile high capacity storage space can be provided to the system.
基金supported by the National Natural Science Foundation of China(Nos.61176093,51072171)
文摘This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital broadcasting system（DBS） standards,including DVB-S,DVB-S2,and ABS-S.The cut-off frequency of the baseband circuit can be changed continuously from 4.5 to 32 MHz.The gain adjustment range is from 6 to 55.5 dB with 0.5 dB step.The calibration includes automatic frequency tuning（AFT） and automatic DC offset calibration （DCOC） to achieve less than 6%cut-off frequency deviation and 3 mV residual output offset.The out-of-band IIP2 and IIP3 of the overall chain are 45 dBm and 18 dBm respectively,while the input referred noise（IRN） is 17.4 nV/√Hz.All circuit blocks are operated at 2.8 V from LDO and consume current of 20.4 mA in the receiving mode.
基金supported by the Scientific Research Plan Projects of Hebei Education Department(No.Q2012019)
文摘This paper presents the design and implementation of a low power wide tuning range baseband filter with an accurate on-chip tuning circuit for reconfigurable multistandard wireless transceivers. The realized low pass filter （LPF） is a six-order Butterworth type by cascading three stage active-Gm-RC biquadratic cells. A mod- ified linearization technique is used to improve the filter linearity performance at low power consumption. A new process-independent transconductor matching circuit and a new frequency tuning circuit with frequency compen- sation are proposed to achieve a high precision filter frequency response. The proposed LPF is realized in a 130 nm standard CMOS technology. The measured results show that the LPF exhibits a high bandwidth programmability from 0.1 to 25 MHz with a tuning frequency error less than 2.68% over the wide tuning range. The power consump- tion is scalable, ranging from 0.52 to 5.25 mA, from a 1.2 V power supply while achieving a 26.3 dBm in-band IIP3.
基金Project supported by the Major National Science&Technology Program of China(No.2009ZX03007-002)the National Natural Science Foundation of China(No.60976022).
文摘An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18/zm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 × 2.6 mm^2 area and consumes 83 mW under typical work modes.
基金supported by the National Natural Science Foundation of China(No.60806008)the Fok Ying Tung Education Foundation, China(No.104028).
文摘A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth in 0.35μm CMOS is presented. The circuit consists of two variable gain amplifiers（VGA） in cascade and a Gm-C elliptic low-pass filter（LPF）. The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption,the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application.Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN,8.9 mW for WCDMA and only 6.5 mW for Bluetooth,all with a 3 V power supply.The analog baseband circuit could provide -10 to ＋40 dB variable gain,third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth,fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN,respectively.
基金Project supported by the Important National Science and Technology Specific Projects of China(No2009ZX01031-003-002)the National High Technology Research and Development Program of China(No2009AA011605)the National Natural Science Foundation of China(No61076028)
文摘This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm;and 0.48×0.25 mm;areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）;according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.
基金Project supported by the Provincial and Ministerial Industry-Academia Cooperation Project of China(No.2009A090100019)
文摘This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.
基金Project supported by the National High Technology Research and Development Program of China(Nos.2009AA01Z261,2009ZX01031- 003 -002 )
文摘A dual-mode analog baseband with digital-assisted DC-offset calibration （DCOC） for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC- offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm^2.
基金Project supported by the Important National Science & Technology Specific Projects(No.2009ZX01031-003-002)the National High Technology Research and Development Program of China(No.2009AA011605)
文摘This paper describes a low-pass reconfigurable baseband filter for GSM, TD-SCDMA and WCDMA multi-mode transmitters. To comply with 3GPP emission mask and limit TX leakage at the RX band, the out- of-band noise performance is optimized. Due to the distortion caused by the subthreshold leakage current of the switches used in capacitor array, a capacitor bypass technique is proposed to improve the filter＇s linearity. An automatic frequency tuning circuit is adopted to compensate the cut-off frequency variation. Simulation results show that the filter achieves an in-band input-referred third-order intercept point （IIP3） of 47 dBm at 1.2-V power supply and the out-of-band noise can meet TX SAW-less requirement for WCDMA ＆ TD-SCDMA. The baseband filter incorporates -40 to 0 dB programmable gain control that is accurately variable in 0.5 dB steps. The filter＇s cut-off frequency can be reconfigured for GSM/TD-SCDMA/WCDMA multi-mode transmitter. The implemented baseband filter draws 3.6 mA from a 1.2-V supply in a 0.13 μm CMOS process.
