A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The ...A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The proposed architecture is investigated with special emphasis on low power and small decoder latency,in which a dedicated register-exchange module is designed to provide tentative survivor symbols with zero latency,and a high-speed trace back logic is presented to meet the tight latency budget specified for 1000BASE-T transceiver.Furthermore,clock-gating register banks are constructed for power saving.VLSI implementation reveals that,the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.展开更多
10BASE-T1L工业以太网技术可以在单对双绞线上实现距离长达1000 m的10 Mb/s的全双工通信带宽,还可通过数据线供电(Power over Data Lines,PoDL)技术给设备提供高达60 W的供电,大大降低了边缘端设备需要分别布置供电和通信线的难度与成...10BASE-T1L工业以太网技术可以在单对双绞线上实现距离长达1000 m的10 Mb/s的全双工通信带宽,还可通过数据线供电(Power over Data Lines,PoDL)技术给设备提供高达60 W的供电,大大降低了边缘端设备需要分别布置供电和通信线的难度与成本。对比工业以太网通信技术与常用工业现场通信总线之间的差异,讲解基于10BASE-T1L工业以太网技术的边缘状态监测单元设计,为后续开展基于10BASE-T1L技术的工业物联网(Internet of Things,IoT)状态监控设备开发提供了借鉴。展开更多
This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the ...This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and l Gb/s throughput in 1.8 V 0.18μm standard cell complementary metal-oxide-semiconductor （CMOS） process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder （PDFD） with 39% area reduction.展开更多
文摘A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The proposed architecture is investigated with special emphasis on low power and small decoder latency,in which a dedicated register-exchange module is designed to provide tentative survivor symbols with zero latency,and a high-speed trace back logic is presented to meet the tight latency budget specified for 1000BASE-T transceiver.Furthermore,clock-gating register banks are constructed for power saving.VLSI implementation reveals that,the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.
文摘10BASE-T1L工业以太网技术可以在单对双绞线上实现距离长达1000 m的10 Mb/s的全双工通信带宽,还可通过数据线供电(Power over Data Lines,PoDL)技术给设备提供高达60 W的供电,大大降低了边缘端设备需要分别布置供电和通信线的难度与成本。对比工业以太网通信技术与常用工业现场通信总线之间的差异,讲解基于10BASE-T1L工业以太网技术的边缘状态监测单元设计,为后续开展基于10BASE-T1L技术的工业物联网(Internet of Things,IoT)状态监控设备开发提供了借鉴。
基金the National Science Foundation for Creative Research Groups （60521002）Shanghai Natural Science Foundation （037062022）.
文摘This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and l Gb/s throughput in 1.8 V 0.18μm standard cell complementary metal-oxide-semiconductor （CMOS） process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder （PDFD） with 39% area reduction.
