The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide ...The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.展开更多
Breakdown voltage （Vbd） and charge to breakdown （Qbd） are two parameters often used to evaluate gate oxide reliability. In this paper,we investigate the effects of measurement methods on Vbd and Qbd of the gate ox...Breakdown voltage （Vbd） and charge to breakdown （Qbd） are two parameters often used to evaluate gate oxide reliability. In this paper,we investigate the effects of measurement methods on Vbd and Qbd of the gate oxide of a 0.18μm dual gate CMOS process. Voltage ramps （V-ramp） and current ramps （J-ramp） are used to evaluate gate oxide reliability. The thin and thick gate oxides are all evaluated in the accumulation condition. Our experimental results show that the measurement methods affect Vbd only slightly but affect Qbd seriously,as do the measurement conditions.This affects the I-t curves obtained with the J-ramp and V-ramp methods. From the I-t curve,it can be seen that Qbd obtained using a J-ramp is much bigger than that with a V-ramp. At the same time, the Weibull slopes of Qbd are definitely smaller than those of Vbd. This means that Vbd is more reliable than Qbd, Thus we should be careful to use Qbd to evaluate the reliability of 0.18μm or beyond CMOS process gate oxide.展开更多
The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tu...The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10^(18) cm^(-3) and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.展开更多
A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations....A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.展开更多
The emission microscopy （EMMI） test is proposed as an effective method to control the polysilicon over-etching time of advanced CMOS processing combined with a novel test structure, named a poly-edge structure. From...The emission microscopy （EMMI） test is proposed as an effective method to control the polysilicon over-etching time of advanced CMOS processing combined with a novel test structure, named a poly-edge structure. From the values of the breakdown voltage （Vbd） of MOS capacitors （poly-edge structure） ,it was observed that,with for the initial polysilicon etching-time, almost all capacitors in one wafer failed under the initial failure model. With the increase of polysilicon over-etching time, the number of the initial failure capacitors decreased. Finally, no initial failure capacitors were observed after the polysilicon over-etching time was increased by 30s. The breakdown samples with the initial failure model and intrinsic failure model underwent EMMI tests. The EMMI test results show that the initial failure of capacitors with poly-edge structures was due to the bridging effect between the silicon substrate and the polysilicon gate caused by the residual polysilicon in the ditch between the shallow-trench isolation region and the active area, which will short the polysilicon gate with silicon substrate after the silicide process.展开更多
碳化硅SiC(silicon carbide)功率器件因其卓越的材料性能,表现出巨大的应用前景,其中金属-氧化物-场效应晶体管MOSFET(metal oxide semiconductor field effect transistor)是最重要的器件。3300 V SiC MOSFET可应用于轨道交通和智能电...碳化硅SiC(silicon carbide)功率器件因其卓越的材料性能,表现出巨大的应用前景,其中金属-氧化物-场效应晶体管MOSFET(metal oxide semiconductor field effect transistor)是最重要的器件。3300 V SiC MOSFET可应用于轨道交通和智能电网等大功率领域,能显著提高效率,降低装置体积。在这些应用领域中,对功率器件的可靠性要求很高,为此,针对自主研制的3300 V SiC MOSFET开展栅氧可靠性研究。首先,按照常规的评估技术对其进行了高温栅偏HTGB(high temperature gate bias)试验;其次,针对高压SiC MOSFET的特点进行了漏源反偏时栅氧电热应力的研究。试验结果表明,在高压SiC MOSFET中,漏源反偏时栅氧的电热应力较大,在设计及使用时应尤为注意。展开更多
文摘The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.
文摘Breakdown voltage （Vbd） and charge to breakdown （Qbd） are two parameters often used to evaluate gate oxide reliability. In this paper,we investigate the effects of measurement methods on Vbd and Qbd of the gate oxide of a 0.18μm dual gate CMOS process. Voltage ramps （V-ramp） and current ramps （J-ramp） are used to evaluate gate oxide reliability. The thin and thick gate oxides are all evaluated in the accumulation condition. Our experimental results show that the measurement methods affect Vbd only slightly but affect Qbd seriously,as do the measurement conditions.This affects the I-t curves obtained with the J-ramp and V-ramp methods. From the I-t curve,it can be seen that Qbd obtained using a J-ramp is much bigger than that with a V-ramp. At the same time, the Weibull slopes of Qbd are definitely smaller than those of Vbd. This means that Vbd is more reliable than Qbd, Thus we should be careful to use Qbd to evaluate the reliability of 0.18μm or beyond CMOS process gate oxide.
基金Project supported by the San Disk Info Tech Shanghai,Chinathe Institute of Microelectronic Materials&Technology,School of Materials Science and Engineering,Shanghai Jiao Tong University,China。
文摘The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10^(18) cm^(-3) and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.
基金the National Natural Science Foundation of China (Grant Nos. 61774052 and 61904045)the National Research and Development Program for Major Research Instruments of China (Grant No. 62027814)the Natural Science Foundation of Jiangxi Province, China (Grant No. 20212BAB214047)。
文摘A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.
文摘The emission microscopy （EMMI） test is proposed as an effective method to control the polysilicon over-etching time of advanced CMOS processing combined with a novel test structure, named a poly-edge structure. From the values of the breakdown voltage （Vbd） of MOS capacitors （poly-edge structure） ,it was observed that,with for the initial polysilicon etching-time, almost all capacitors in one wafer failed under the initial failure model. With the increase of polysilicon over-etching time, the number of the initial failure capacitors decreased. Finally, no initial failure capacitors were observed after the polysilicon over-etching time was increased by 30s. The breakdown samples with the initial failure model and intrinsic failure model underwent EMMI tests. The EMMI test results show that the initial failure of capacitors with poly-edge structures was due to the bridging effect between the silicon substrate and the polysilicon gate caused by the residual polysilicon in the ditch between the shallow-trench isolation region and the active area, which will short the polysilicon gate with silicon substrate after the silicide process.
文摘碳化硅SiC(silicon carbide)功率器件因其卓越的材料性能,表现出巨大的应用前景,其中金属-氧化物-场效应晶体管MOSFET(metal oxide semiconductor field effect transistor)是最重要的器件。3300 V SiC MOSFET可应用于轨道交通和智能电网等大功率领域,能显著提高效率,降低装置体积。在这些应用领域中,对功率器件的可靠性要求很高,为此,针对自主研制的3300 V SiC MOSFET开展栅氧可靠性研究。首先,按照常规的评估技术对其进行了高温栅偏HTGB(high temperature gate bias)试验;其次,针对高压SiC MOSFET的特点进行了漏源反偏时栅氧电热应力的研究。试验结果表明,在高压SiC MOSFET中,漏源反偏时栅氧的电热应力较大,在设计及使用时应尤为注意。
