Far-field wireless power transfer(WPT)is a major breakthrough technology that will enable the many anticipated ubiquitous Internet of Things(IoT)applications associated with fifth generation(5G),sixth generation(6G),a...Far-field wireless power transfer(WPT)is a major breakthrough technology that will enable the many anticipated ubiquitous Internet of Things(IoT)applications associated with fifth generation(5G),sixth generation(6G),and beyond wireless ecosystems.Rectennas,which are the combination of rectifying circuits and antennas,are the most critical components in far-field WPT systems.However,compact application devices require even smaller integrated rectennas that simultaneously have large electromagnetic wave capture capabilities,high alternating current(AC)-to-direct current(DC)(AC-to-DC)conversion efficiencies,and facilitate a multifunctional wireless performance.This paper reviews various rectenna miniaturization techniques such as meandered planar inverted-F antenna(PIFA)rectennas;miniaturized monopole-and dipole-based rectennas;fractal loop and patch rectennas;dielectric-loaded rectennas;and electrically small near-field resonant parasitic rectennas.Their performance characteristics are summarized and then compared with our previously developed electrically small Huygens rectennas that are proven to be more suitable for IoT applications.They have been tailored,for example,to achieve batteryfree IoT sensors as is demonstrated in this paper.Battery-free,wirelessly powered devices are smaller and lighter in weight in comparison to battery-powered devices.Moreover,they are environmentally friendly and,hence,have a significant societal benefit.A series of high-performance electrically small Huygens rectennas are presented including Huygens linearly-polarized(HLP)and circularly-polarized(HCP)rectennas;wirelessly powered IoT sensors based on these designs;and a dual-functional HLP rectenna and antenna system.Finally,two linear uniform HLP rectenna array systems are considered for significantly larger wireless power capture.Example arrays illustrate how they can be integrated advantageously with DC or radio frequency(RF)power-combining schemes for practical IoT applications.展开更多
Array of Things (AoT)通过单一位置上的多传感器对城市系统进行连续动态观测。AoT观测数据量大且持续增长,使得如何利用有限的计算资源进行AoT序列数据的压缩传输成为其应用的关键瓶颈之一。本文提出了一种基于张量分解的AoT序列数据...Array of Things (AoT)通过单一位置上的多传感器对城市系统进行连续动态观测。AoT观测数据量大且持续增长,使得如何利用有限的计算资源进行AoT序列数据的压缩传输成为其应用的关键瓶颈之一。本文提出了一种基于张量分解的AoT序列数据的有损压缩方法。面向其海量、高维且需在传感器端处理的需求,该方法首先将AoT序列数据组织成高维张量,利用算法复杂度较低的张量CANDECOMP/PARAFAC (CP)分解提取各维度上的特征主分量,而后利用张量重构实现特征保持的数据有损压缩。利用基于张量分解的有损压缩方法,针对美国芝加哥市区的24 h内感测的声光电磁数据进行了实验,讨论了不同压缩参数对压缩比、压缩误差、压缩精度、压缩时间、压缩过程运行内存占用和压缩结果内存占用之间的影响。实验结果表明该方法可实现AoT序列数据的有损压缩,其较小的内存占用能够支持传感器端数据压缩。并且与原始光场强度对比表明,压缩后的数据保持了原有时空分布特征。与传统矢量量化编码压缩方法相比,在相同压缩精度下,本文方法的压缩比约高27%~76%,压缩时间约节省46%~73%,压缩结果所占内存约节省17%~57%,因此本文方法具有更高的压缩比,更低的压缩时间和内存占用,可为Ao T这一类数据的大规模有损压缩提供借鉴意义。展开更多
The rapid development of internet of things(loT)urgently needs edge miniaturized computing devices with high efficiency and low-power consumption.In-sensor computing has emerged as a promising technology to enable in-...The rapid development of internet of things(loT)urgently needs edge miniaturized computing devices with high efficiency and low-power consumption.In-sensor computing has emerged as a promising technology to enable in-situ data processing within the sensor array.Here,we report an optoelectronic array for in-sensor computing by integrating photodiodes(PDs)with resistive random-access memories(RRAMs).The PD-RRAM unit cell exhibits reconfigurable optoelectronic output and photo-responsivity by programming RRAMs into different resistance states.Furthermore,a 3×3 PD-RRAM array is fabricated to demonstrate optical image recognition,achieving a universal architecture with ultralow latency and low power consumption.This study highlights the great potential of the PD-RRAM optoelectronic array as an energy-effcient in-sensor computing primitive for future IoT applications.展开更多
Artificial intelligence of things systems equipped with flexible sensors can autonomously and intelligently detect the condition of the surroundings.However,current intelligent monitoring systems always rely on an ext...Artificial intelligence of things systems equipped with flexible sensors can autonomously and intelligently detect the condition of the surroundings.However,current intelligent monitoring systems always rely on an external computer with the capability of machine learning rather than integrating it into the sensing device.The computer-assisted intelligent system is hampered by energy inefficiencies,privacy issues,and bandwidth restrictions.Here,a flexible,large-scale sensing array with the capability of low-power in-sensor intelligence based on a compression hypervector encoder is proposed for real-time recognition.The system with in-sensor intelligence can accommodate different individuals and learn new postures without additional computer processing.Both the communication bandwidth requirement and energy consumption of this system are significantly reduced by 1,024 and 500 times,respectively.The capability for in-sensor inference and learning eliminates the necessity to transmit raw data externally,thereby effectively addressing privacy concerns.Furthermore,the system possesses a rapid recognition speed(a few hundred milliseconds)and a high recognition accuracy(about 99%),comparing with support vector machine and other hyperdimensional computing methods.The research holds marked potential for applications in the integration of artificial intelligence of things and flexible electronics.展开更多
To tackle the challenge of applying convolutional neural network(CNN)in field-programmable gate array(FPGA)due to its computational complexity,a high-performance CNN hardware accelerator based on Verilog hardware desc...To tackle the challenge of applying convolutional neural network(CNN)in field-programmable gate array(FPGA)due to its computational complexity,a high-performance CNN hardware accelerator based on Verilog hardware description language was designed,which utilizes a pipeline architecture with three parallel dimensions including input channels,output channels,and convolution kernels.Firstly,two multiply-and-accumulate(MAC)operations were packed into one digital signal processing(DSP)block of FPGA to double the computation rate of the CNN accelerator.Secondly,strategies of feature map block partitioning and special memory arrangement were proposed to optimize the total amount of off-chip access memory and reduce the pressure on FPGA bandwidth.Finally,an efficient computational array combining multiplicative-additive tree and Winograd fast convolution algorithm was designed to balance hardware resource consumption and computational performance.The high parallel CNN accelerator was deployed in ZU3 EG of Alinx,using the YOLOv3-tiny algorithm as the test object.The average computing performance of the CNN accelerator is 127.5 giga operations per second(GOPS).The experimental results show that the hardware architecture effectively improves the computational power of CNN and provides better performance compared with other existing schemes in terms of power consumption and the efficiency of DSPs and block random access memory(BRAMs).展开更多
基金supported by the University of Technology Sydney (UTS) Chancellor’s Postdoctoral Fellowship (PRO18-6147)Australian Research Council (ARC) Discovery Early Career Researcher Award (DECRA) (PRO20-9959)
文摘Far-field wireless power transfer(WPT)is a major breakthrough technology that will enable the many anticipated ubiquitous Internet of Things(IoT)applications associated with fifth generation(5G),sixth generation(6G),and beyond wireless ecosystems.Rectennas,which are the combination of rectifying circuits and antennas,are the most critical components in far-field WPT systems.However,compact application devices require even smaller integrated rectennas that simultaneously have large electromagnetic wave capture capabilities,high alternating current(AC)-to-direct current(DC)(AC-to-DC)conversion efficiencies,and facilitate a multifunctional wireless performance.This paper reviews various rectenna miniaturization techniques such as meandered planar inverted-F antenna(PIFA)rectennas;miniaturized monopole-and dipole-based rectennas;fractal loop and patch rectennas;dielectric-loaded rectennas;and electrically small near-field resonant parasitic rectennas.Their performance characteristics are summarized and then compared with our previously developed electrically small Huygens rectennas that are proven to be more suitable for IoT applications.They have been tailored,for example,to achieve batteryfree IoT sensors as is demonstrated in this paper.Battery-free,wirelessly powered devices are smaller and lighter in weight in comparison to battery-powered devices.Moreover,they are environmentally friendly and,hence,have a significant societal benefit.A series of high-performance electrically small Huygens rectennas are presented including Huygens linearly-polarized(HLP)and circularly-polarized(HCP)rectennas;wirelessly powered IoT sensors based on these designs;and a dual-functional HLP rectenna and antenna system.Finally,two linear uniform HLP rectenna array systems are considered for significantly larger wireless power capture.Example arrays illustrate how they can be integrated advantageously with DC or radio frequency(RF)power-combining schemes for practical IoT applications.
文摘Array of Things (AoT)通过单一位置上的多传感器对城市系统进行连续动态观测。AoT观测数据量大且持续增长,使得如何利用有限的计算资源进行AoT序列数据的压缩传输成为其应用的关键瓶颈之一。本文提出了一种基于张量分解的AoT序列数据的有损压缩方法。面向其海量、高维且需在传感器端处理的需求,该方法首先将AoT序列数据组织成高维张量,利用算法复杂度较低的张量CANDECOMP/PARAFAC (CP)分解提取各维度上的特征主分量,而后利用张量重构实现特征保持的数据有损压缩。利用基于张量分解的有损压缩方法,针对美国芝加哥市区的24 h内感测的声光电磁数据进行了实验,讨论了不同压缩参数对压缩比、压缩误差、压缩精度、压缩时间、压缩过程运行内存占用和压缩结果内存占用之间的影响。实验结果表明该方法可实现AoT序列数据的有损压缩,其较小的内存占用能够支持传感器端数据压缩。并且与原始光场强度对比表明,压缩后的数据保持了原有时空分布特征。与传统矢量量化编码压缩方法相比,在相同压缩精度下,本文方法的压缩比约高27%~76%,压缩时间约节省46%~73%,压缩结果所占内存约节省17%~57%,因此本文方法具有更高的压缩比,更低的压缩时间和内存占用,可为Ao T这一类数据的大规模有损压缩提供借鉴意义。
基金the National Key Research and Development Program(2021YFA0716400)the National Natural Science Foundation of China(62225405,62350002,61991443,62127814,62235005,and 61927811)the Collaborative Innovation Center of Solid-State Lighting and Energy-Saving Electronics。
文摘The rapid development of internet of things(loT)urgently needs edge miniaturized computing devices with high efficiency and low-power consumption.In-sensor computing has emerged as a promising technology to enable in-situ data processing within the sensor array.Here,we report an optoelectronic array for in-sensor computing by integrating photodiodes(PDs)with resistive random-access memories(RRAMs).The PD-RRAM unit cell exhibits reconfigurable optoelectronic output and photo-responsivity by programming RRAMs into different resistance states.Furthermore,a 3×3 PD-RRAM array is fabricated to demonstrate optical image recognition,achieving a universal architecture with ultralow latency and low power consumption.This study highlights the great potential of the PD-RRAM optoelectronic array as an energy-effcient in-sensor computing primitive for future IoT applications.
基金supported by the National Key R&D Program of China(grant no.2020YFA0405700)the NationalNatural Science Foundation of China(grant no.51925503 to Y.H.and grant no.52375568 to F.Z.)+1 种基金the Tencent Foundation(XPLORER Prize to Y.H.)the Science and Technology Innovation Team of Hubei Province.
文摘Artificial intelligence of things systems equipped with flexible sensors can autonomously and intelligently detect the condition of the surroundings.However,current intelligent monitoring systems always rely on an external computer with the capability of machine learning rather than integrating it into the sensing device.The computer-assisted intelligent system is hampered by energy inefficiencies,privacy issues,and bandwidth restrictions.Here,a flexible,large-scale sensing array with the capability of low-power in-sensor intelligence based on a compression hypervector encoder is proposed for real-time recognition.The system with in-sensor intelligence can accommodate different individuals and learn new postures without additional computer processing.Both the communication bandwidth requirement and energy consumption of this system are significantly reduced by 1,024 and 500 times,respectively.The capability for in-sensor inference and learning eliminates the necessity to transmit raw data externally,thereby effectively addressing privacy concerns.Furthermore,the system possesses a rapid recognition speed(a few hundred milliseconds)and a high recognition accuracy(about 99%),comparing with support vector machine and other hyperdimensional computing methods.The research holds marked potential for applications in the integration of artificial intelligence of things and flexible electronics.
基金supported by the National Natural Science Foundation of China(61871132,62171135)。
文摘To tackle the challenge of applying convolutional neural network(CNN)in field-programmable gate array(FPGA)due to its computational complexity,a high-performance CNN hardware accelerator based on Verilog hardware description language was designed,which utilizes a pipeline architecture with three parallel dimensions including input channels,output channels,and convolution kernels.Firstly,two multiply-and-accumulate(MAC)operations were packed into one digital signal processing(DSP)block of FPGA to double the computation rate of the CNN accelerator.Secondly,strategies of feature map block partitioning and special memory arrangement were proposed to optimize the total amount of off-chip access memory and reduce the pressure on FPGA bandwidth.Finally,an efficient computational array combining multiplicative-additive tree and Winograd fast convolution algorithm was designed to balance hardware resource consumption and computational performance.The high parallel CNN accelerator was deployed in ZU3 EG of Alinx,using the YOLOv3-tiny algorithm as the test object.The average computing performance of the CNN accelerator is 127.5 giga operations per second(GOPS).The experimental results show that the hardware architecture effectively improves the computational power of CNN and provides better performance compared with other existing schemes in terms of power consumption and the efficiency of DSPs and block random access memory(BRAMs).
