为满足车载显示设备低成本、小体积、高性能以及高可靠性的要求,提出了一种基于片上可编程系统SOPC(System On a Programmable Chip)和乒乓存储显示技术的车载信息终端设计。以现场可编程门阵列FPGA(Field Programmable Gate Array)作...为满足车载显示设备低成本、小体积、高性能以及高可靠性的要求,提出了一种基于片上可编程系统SOPC(System On a Programmable Chip)和乒乓存储显示技术的车载信息终端设计。以现场可编程门阵列FPGA(Field Programmable Gate Array)作为硬件载体,构建了基于PowerPC软处理器的液晶显示器LCD(Liquid CrystalDisplay)控制单元,并以电子控制单元ECU(Electronic Control Unit)的形式接入到汽车自动控制系统中,形成具有汽车状态的监测与存储功能的人机交互系统。对系统进行了时序与功能仿真,并通过了硬件平台的测试。实验数据表明,该系统可以实时显示行车信息并提供流畅的视觉体验。展开更多
First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implem...First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.展开更多
文摘为满足车载显示设备低成本、小体积、高性能以及高可靠性的要求,提出了一种基于片上可编程系统SOPC(System On a Programmable Chip)和乒乓存储显示技术的车载信息终端设计。以现场可编程门阵列FPGA(Field Programmable Gate Array)作为硬件载体,构建了基于PowerPC软处理器的液晶显示器LCD(Liquid CrystalDisplay)控制单元,并以电子控制单元ECU(Electronic Control Unit)的形式接入到汽车自动控制系统中,形成具有汽车状态的监测与存储功能的人机交互系统。对系统进行了时序与功能仿真,并通过了硬件平台的测试。实验数据表明,该系统可以实时显示行车信息并提供流畅的视觉体验。
文摘First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.
