WDTU(Wireless Data Terminal Unit)是实现将数据通过无线网络(GPRS/CDMA)传输到以太网上数据中心的终端设备。在本设计中,利用ASIXOS丰富的协议资源及其对DNS功能的支持,结合花生壳客户端软件,使WDTU实现了DNS功能,提高了该终端设备的...WDTU(Wireless Data Terminal Unit)是实现将数据通过无线网络(GPRS/CDMA)传输到以太网上数据中心的终端设备。在本设计中,利用ASIXOS丰富的协议资源及其对DNS功能的支持,结合花生壳客户端软件,使WDTU实现了DNS功能,提高了该终端设备的灵活性,方便了用户的使用,而且扩大了设备的适用范围,提高了产品的竞争力。展开更多
文中论述在复杂嵌入式系统中建立文件系统的重要性．并提出将FATl6文件系统应用于嵌入式操作系统ASIX OS Ⅱ的方案。根据FATl6文件系统总体的构架、基本的数据结构，针对嵌入式系统的特点搭建能够有效管理、读取数据文件的系统。其技术...文中论述在复杂嵌入式系统中建立文件系统的重要性．并提出将FATl6文件系统应用于嵌入式操作系统ASIX OS Ⅱ的方案。根据FATl6文件系统总体的构架、基本的数据结构，针对嵌入式系统的特点搭建能够有效管理、读取数据文件的系统。其技术成熟，应用可靠，并且提供和ASIX OS Ⅱ的API接口，便于使用，易于移植。展开更多
With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a C...With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip （SoC） based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18-μm 1P6M Salicide CMOS process, the area is 7.825 mm x 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.展开更多
文摘WDTU(Wireless Data Terminal Unit)是实现将数据通过无线网络(GPRS/CDMA)传输到以太网上数据中心的终端设备。在本设计中,利用ASIXOS丰富的协议资源及其对DNS功能的支持,结合花生壳客户端软件,使WDTU实现了DNS功能,提高了该终端设备的灵活性,方便了用户的使用,而且扩大了设备的适用范围,提高了产品的竞争力。
文摘文中论述在复杂嵌入式系统中建立文件系统的重要性．并提出将FATl6文件系统应用于嵌入式操作系统ASIX OS Ⅱ的方案。根据FATl6文件系统总体的构架、基本的数据结构，针对嵌入式系统的特点搭建能够有效管理、读取数据文件的系统。其技术成熟，应用可靠，并且提供和ASIX OS Ⅱ的API接口，便于使用，易于移植。
基金funded by the "333 Engineering" Assistance Project of Jiangsu Province,China (No. BRA2011115)
文摘With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip （SoC） based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18-μm 1P6M Salicide CMOS process, the area is 7.825 mm x 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.
