A low-power, high-FoM （figure of merit）, time-domain VCO （voltage controlled oscillator）-based ADC （analog-to-digital converter） in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator （ASDM...A low-power, high-FoM （figure of merit）, time-domain VCO （voltage controlled oscillator）-based ADC （analog-to-digital converter） in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator （ASDM） is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR （exclusive-OR） gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic- distortion-cancellation technique to its transconductance stage, which increases the SNDR （signal to noise and distortion ratio） performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO＇s V-F （voltage to frequency） conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC＇s low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.展开更多
文摘A low-power, high-FoM （figure of merit）, time-domain VCO （voltage controlled oscillator）-based ADC （analog-to-digital converter） in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator （ASDM） is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR （exclusive-OR） gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic- distortion-cancellation technique to its transconductance stage, which increases the SNDR （signal to noise and distortion ratio） performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO＇s V-F （voltage to frequency） conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC＇s low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.
