The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field represen...The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field representations and Boolean Satisfiability(SAT)solvers.Our research makes several significant contri-butions to the field.Firstly,we have optimized the GF(24)inversion,achieving a remarkable 31.35%area reduction(15.33 GE)compared to the best known implementations.Secondly,we have enhanced multiplication implementa-tions for transformation matrices using a SAT-method based on local solutions.This approach has yielded notable improvements,such as a 22.22%reduction in area(42.00 GE)for the top transformation matrix in GF((24)2)-type S-box implementation.Furthermore,we have proposed new implementations of GF(((22)2)2)-type and GF((24)2)-type S-boxes,with the GF(((22)2)2)-type demonstrating superior performance.This implementation offers two variants:a small area variant that sets new area records,and a fast variant that establishes new benchmarks in Area-Execution-Time(AET)and energy consumption.Our approach significantly improves upon existing S-box implementations,offering advancements in area,speed,and energy consumption.These optimizations contribute to more efficient and secure AES implementations,potentially enhancing various cryptographic applications in the field of network security.展开更多
Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and ...Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and high throughput advantage.We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm,whereas these are rarely applied to this field.Among the available encryption algorithms,the advanced encryption standard(AES)algorithm is an advanced encryption standard algorithm.It is currently the most widely used symmetric cryptography algorithm.In this work,we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb0_(3) process.We design an AES S-box circuit in the RSFQ logic,and compare its operational frequency,power dissipation,and throughput with those of the CMOS-based circuit post-simulated in the same structure.The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz.Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box.Further,we design and fabricate a few typical modules of the S-box.Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.展开更多
A side-channel attack(SCA)-resistant AES S-box implementation is proposed,which is an improvement from the power-aware hiding(PAH)S-box but with higher security and a smaller area.We use the composite field approach a...A side-channel attack(SCA)-resistant AES S-box implementation is proposed,which is an improvement from the power-aware hiding(PAH)S-box but with higher security and a smaller area.We use the composite field approach and apply the PAH method to the inversion in the nonlinear kernel and a masking method to the other parts.In addition,a delaymatched enable control technique is used to suppress glitches in the masked parts.The evaluation results show that its area is contracted to 63.3%of the full PAH S-box,and its power-delay product is much lower than that of the masking implementation.The leakage assessment using simulation power traces concludes that it has no detectable leakage under t-test and that it at least can thwart the moment-correlation analysis using 665000 noiseless traces.展开更多
To obtain a low-power and compact implementation of the advanced encryption standard （AES） S- box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S...To obtain a low-power and compact implementation of the advanced encryption standard （AES） S- box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S-box, some improvements were made as follows. （1） Level-sensitive latches were inserted in data path to block the propagation Of the dynamic hazards, which lowered the power of data path circuit. （2） Operations of latches were controlled by latch controllers based on presented asynchronous sequence element： LC-element, which utilized static asymmetric C-element to construct a simple and power-efficient circuit structure. （3） Implementation of the data path circuit was a semi-custom standard-cell circuit on 0.25μm complementary mental oxide semiconductor （CMOS） process; and the full-custom design methodology was adopted in the handshake circuit design. Experimental results show that the resulting circuit achieves nearly 46% improvement with moderate area penalty （ 11.7% ） compared with the related composite field S-box in power performance. The presented S-box circuit can be a hardware intelli-gent property （IP） embedded in the targeted systems such as wireless sensor networks （WSN）, smart-cards and radio frequency identification （RFID）.展开更多
Substitution boxes (S-Boxes) in advanced encryption standard (AES) are vulnerable to attacks bypower analysis.The general S-Boxes masking schemes in circuit level need to adjust the design flow andlibrary databases.Th...Substitution boxes (S-Boxes) in advanced encryption standard (AES) are vulnerable to attacks bypower analysis.The general S-Boxes masking schemes in circuit level need to adjust the design flow andlibrary databases.The masking strategies in algorithm level view each S-Box as an independent moduleand mask them respectively,which are costly in size and power for non-linear characteristic of S-Boxes.The new method uses dynamic inhomogeneous S-Boxes instead of traditional homogeneous S-Boxes,andarranges the S-Boxes randomly.So the power and data path delay of substitution unit become unpre-dictable.The experimental results demonstrate that this scheme takes advantages of the circuit character-istics of various S-Box implementations to eliminate the correlation between crypto operation and power.Itneeds less extra circuits and suits resource constrained applications.展开更多
The growing market of WPAN has led to an increasingdemand of security measures and devices forprotecting the user data transmitted over the openchannels.Advanced Encryption Standards(AES)isthe basic security approach ...The growing market of WPAN has led to an increasingdemand of security measures and devices forprotecting the user data transmitted over the openchannels.Advanced Encryption Standards(AES)isthe basic security approach for WPAN.To meet thelow cost,low power feature and high security demandof WPAN,a low cost,high efficient AES coreis proposed in this paper.To achieve low cost,methods of integration and resource sharing are usedin designing a very low-complexity architecture,especially in(inverse)byte substitution(inv)SubBytes)modules and(inverse)mix column(inv)MixColumn)modules,etc.Further more,AESEncryptor and Decryptor is integrated into a fullfunctional crypto-engine.This very low-cost andhigh efficiency AES core of IEEE 802.15.4-2006 isdesigned and emulated on Xilinx FPGA.Simulationresults show that this kind of design can be used inresource critical applications,such as smart card,PDA and mobile phones.展开更多
The implementation of small size cryptography algorithm is a critical problem for wireless sensor network. A low cost compact intellectual property （IP） core of the entire advanced encryption standard （AES） algori...The implementation of small size cryptography algorithm is a critical problem for wireless sensor network. A low cost compact intellectual property （IP） core of the entire advanced encryption standard （AES） algorithm for wireless sensor network is presented in this paper. A compact encryption and decryption system using only four sharing S-Boxes is obtained, employing sharing between the encryption and decryption processes. Our design proposes use of composite field data path for the SubBytes and InvSubBytes transformations. With an implementation of the AES block cipher with Virtex Ⅱ Pro FPGA using0.13μm and 90nm process technology, our area optimized consumes 16.8k equivalent gates. The speed of this implementation is also reduced to 0.45Gbits/s. Compared with previous implementations, our design achieves significant low-cost area with acceptable throughput.展开更多
It is crucial to design energy-efficient advanced encryption standard （AES） cryptography for low power embedded systems powered by limited battery. Since the S-Boxes consume much of the total AES circuit power, an e...It is crucial to design energy-efficient advanced encryption standard （AES） cryptography for low power embedded systems powered by limited battery. Since the S-Boxes consume much of the total AES circuit power, an efficient approach to reducing the AES power consumption consists in reducing the S-Boxes power consumption. Among various implementations of S-Boxes, the most energy-efficient one is the decoder-switchencoder （DSE） architecture. In this paper, we refine the DSE architecture and propose one faster, more compact S-Boxes architecture of lower power： an improved and full-balanced DSE architecture. This architecture achieves low power consumption of 68 μW at 10 MHz using 0.25 ktm 1.SV UMC CMOS technology. Compared with the original DSE S-Boxes, it further reduces the delay, gate count and power consumption by 8%, 14% and 10% respect/vely. At the sane time, simulation results show that the improved DSE S-Boxes has the best performance among various S-Boxes architectures in terms of power-area product and power-delay product, and it is optimal for implementing low power AES cryptography.展开更多
基金supported in part by the National Natural Science Foundation of China(No.62162016)in part by the Innovation Project of Guangxi Graduate Education(Nos.YCBZ2023132 and YCSW2023304).
文摘The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field representations and Boolean Satisfiability(SAT)solvers.Our research makes several significant contri-butions to the field.Firstly,we have optimized the GF(24)inversion,achieving a remarkable 31.35%area reduction(15.33 GE)compared to the best known implementations.Secondly,we have enhanced multiplication implementa-tions for transformation matrices using a SAT-method based on local solutions.This approach has yielded notable improvements,such as a 22.22%reduction in area(42.00 GE)for the top transformation matrix in GF((24)2)-type S-box implementation.Furthermore,we have proposed new implementations of GF(((22)2)2)-type and GF((24)2)-type S-boxes,with the GF(((22)2)2)-type demonstrating superior performance.This implementation offers two variants:a small area variant that sets new area records,and a fast variant that establishes new benchmarks in Area-Execution-Time(AET)and energy consumption.Our approach significantly improves upon existing S-box implementations,offering advancements in area,speed,and energy consumption.These optimizations contribute to more efficient and secure AES implementations,potentially enhancing various cryptographic applications in the field of network security.
基金This work was supported by the National Natural Science Foundation of China(Grant No.92164101)the National Natural Science Foundation of China(Grant No.62171437)+2 种基金the Strategic Priority Research Program of the Chinese Academy of Sciences(Grant No.XDA18000000)Shanghai Science and Technology Committee(Grant No.21DZ1101000)the National Key R&D Program of China(Grant No.2021YFB0300400).
文摘Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and high throughput advantage.We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm,whereas these are rarely applied to this field.Among the available encryption algorithms,the advanced encryption standard(AES)algorithm is an advanced encryption standard algorithm.It is currently the most widely used symmetric cryptography algorithm.In this work,we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb0_(3) process.We design an AES S-box circuit in the RSFQ logic,and compare its operational frequency,power dissipation,and throughput with those of the CMOS-based circuit post-simulated in the same structure.The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz.Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box.Further,we design and fabricate a few typical modules of the S-box.Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.
基金This work was supported by the National Science and Technology Major Project of China(2017ZX01030301).
文摘A side-channel attack(SCA)-resistant AES S-box implementation is proposed,which is an improvement from the power-aware hiding(PAH)S-box but with higher security and a smaller area.We use the composite field approach and apply the PAH method to the inversion in the nonlinear kernel and a masking method to the other parts.In addition,a delaymatched enable control technique is used to suppress glitches in the masked parts.The evaluation results show that its area is contracted to 63.3%of the full PAH S-box,and its power-delay product is much lower than that of the masking implementation.The leakage assessment using simulation power traces concludes that it has no detectable leakage under t-test and that it at least can thwart the moment-correlation analysis using 665000 noiseless traces.
基金the National High Technology Research and Development Programme of China(Grant No2006AA01Z226)the Project(Grant No2006Z001B)the Scientific Research Foundation of Huazhong University of Science and Technology
文摘To obtain a low-power and compact implementation of the advanced encryption standard （AES） S- box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S-box, some improvements were made as follows. （1） Level-sensitive latches were inserted in data path to block the propagation Of the dynamic hazards, which lowered the power of data path circuit. （2） Operations of latches were controlled by latch controllers based on presented asynchronous sequence element： LC-element, which utilized static asymmetric C-element to construct a simple and power-efficient circuit structure. （3） Implementation of the data path circuit was a semi-custom standard-cell circuit on 0.25μm complementary mental oxide semiconductor （CMOS） process; and the full-custom design methodology was adopted in the handshake circuit design. Experimental results show that the resulting circuit achieves nearly 46% improvement with moderate area penalty （ 11.7% ） compared with the related composite field S-box in power performance. The presented S-box circuit can be a hardware intelli-gent property （IP） embedded in the targeted systems such as wireless sensor networks （WSN）, smart-cards and radio frequency identification （RFID）.
基金the National High Technology Research and Development Programme of China(No.2006AA01Z226)
文摘Substitution boxes (S-Boxes) in advanced encryption standard (AES) are vulnerable to attacks bypower analysis.The general S-Boxes masking schemes in circuit level need to adjust the design flow andlibrary databases.The masking strategies in algorithm level view each S-Box as an independent moduleand mask them respectively,which are costly in size and power for non-linear characteristic of S-Boxes.The new method uses dynamic inhomogeneous S-Boxes instead of traditional homogeneous S-Boxes,andarranges the S-Boxes randomly.So the power and data path delay of substitution unit become unpre-dictable.The experimental results demonstrate that this scheme takes advantages of the circuit character-istics of various S-Box implementations to eliminate the correlation between crypto operation and power.Itneeds less extra circuits and suits resource constrained applications.
文摘The growing market of WPAN has led to an increasingdemand of security measures and devices forprotecting the user data transmitted over the openchannels.Advanced Encryption Standards(AES)isthe basic security approach for WPAN.To meet thelow cost,low power feature and high security demandof WPAN,a low cost,high efficient AES coreis proposed in this paper.To achieve low cost,methods of integration and resource sharing are usedin designing a very low-complexity architecture,especially in(inverse)byte substitution(inv)SubBytes)modules and(inverse)mix column(inv)MixColumn)modules,etc.Further more,AESEncryptor and Decryptor is integrated into a fullfunctional crypto-engine.This very low-cost andhigh efficiency AES core of IEEE 802.15.4-2006 isdesigned and emulated on Xilinx FPGA.Simulationresults show that this kind of design can be used inresource critical applications,such as smart card,PDA and mobile phones.
文摘The implementation of small size cryptography algorithm is a critical problem for wireless sensor network. A low cost compact intellectual property （IP） core of the entire advanced encryption standard （AES） algorithm for wireless sensor network is presented in this paper. A compact encryption and decryption system using only four sharing S-Boxes is obtained, employing sharing between the encryption and decryption processes. Our design proposes use of composite field data path for the SubBytes and InvSubBytes transformations. With an implementation of the AES block cipher with Virtex Ⅱ Pro FPGA using0.13μm and 90nm process technology, our area optimized consumes 16.8k equivalent gates. The speed of this implementation is also reduced to 0.45Gbits/s. Compared with previous implementations, our design achieves significant low-cost area with acceptable throughput.
基金the Hi-Tech Research and Development Program of China（2006AA01Z226）； HUST-SRF（2006Z011B）； Program for New Century Excellent Talents in University and the Natural Science Foundation of Hubei（2006ABA080）.
文摘It is crucial to design energy-efficient advanced encryption standard （AES） cryptography for low power embedded systems powered by limited battery. Since the S-Boxes consume much of the total AES circuit power, an efficient approach to reducing the AES power consumption consists in reducing the S-Boxes power consumption. Among various implementations of S-Boxes, the most energy-efficient one is the decoder-switchencoder （DSE） architecture. In this paper, we refine the DSE architecture and propose one faster, more compact S-Boxes architecture of lower power： an improved and full-balanced DSE architecture. This architecture achieves low power consumption of 68 μW at 10 MHz using 0.25 ktm 1.SV UMC CMOS technology. Compared with the original DSE S-Boxes, it further reduces the delay, gate count and power consumption by 8%, 14% and 10% respect/vely. At the sane time, simulation results show that the improved DSE S-Boxes has the best performance among various S-Boxes architectures in terms of power-area product and power-delay product, and it is optimal for implementing low power AES cryptography.
