A novel charge exchanging compensation （CEC） technique is proposed for a wideband sample-and-hold （S/H） circuit applied in an IF sampling ADC. The CEC technique compensates the sampling bandwidth by eliminating th...A novel charge exchanging compensation （CEC） technique is proposed for a wideband sample-and-hold （S/H） circuit applied in an IF sampling ADC. The CEC technique compensates the sampling bandwidth by eliminating the impact from finite on-resistance of the sampling switch, and avoids increasing clock feedthrough and charge injection. Meanwhile, a low power two stage OTA with a class AB output stage is designed to provide the S/H a 3Vp-p input range under 1.8V power. The S/H achieves a 94dB spurious-free dynamic range for a 200MHz input signal at a 100Ms/s sample rate and consumes only 26mW with a 5.5pF load.展开更多
To satisfy the design requirements of analog-to-digital converter （ADC） of high speed sampling system in an infrared focal plane array tester with 1024 × 1024 pixels, a first inter-stage amplifier of 12-bit 40-...To satisfy the design requirements of analog-to-digital converter （ADC） of high speed sampling system in an infrared focal plane array tester with 1024 × 1024 pixels, a first inter-stage amplifier of 12-bit 40- Msample/s pipelined ADC was designed with 0. 35 μm CMOS technology. On the basis of traditional two-stage amplifier, the cross-coupled class AB output stage and cascode compensation were adopted to improve the output vohage swing and bandwidth. Power dissipation was optimized with math tools. Circuit and layout design were completed. Simulation results show that the designed amplifier has good performance of 95 dB dc gain, ±2 V output voltage swing, 190 MHz bandwidth and 63° phase margin with feedback factor 1/4, 33 mW power dissipation and so on, which can meet the system requirements.展开更多
This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with...This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.展开更多
A novel class-AB implementation of a current-mode programmable gain amplifier （CPGA） including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides ...A novel class-AB implementation of a current-mode programmable gain amplifier （CPGA） including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.展开更多
A novel matching method between the power amplifier （PA） and antenna of an active or semi-active RFID tag is presented. A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The t...A novel matching method between the power amplifier （PA） and antenna of an active or semi-active RFID tag is presented. A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240 × 70 μm^2 in a 0.18μm CMOS process due to saving two on-chip integrated inductors. Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal, the PA shows a measured output power of 8 dBm at the 1 dB compression point.展开更多
文摘A novel charge exchanging compensation （CEC） technique is proposed for a wideband sample-and-hold （S/H） circuit applied in an IF sampling ADC. The CEC technique compensates the sampling bandwidth by eliminating the impact from finite on-resistance of the sampling switch, and avoids increasing clock feedthrough and charge injection. Meanwhile, a low power two stage OTA with a class AB output stage is designed to provide the S/H a 3Vp-p input range under 1.8V power. The S/H achieves a 94dB spurious-free dynamic range for a 200MHz input signal at a 100Ms/s sample rate and consumes only 26mW with a 5.5pF load.
文摘To satisfy the design requirements of analog-to-digital converter （ADC） of high speed sampling system in an infrared focal plane array tester with 1024 × 1024 pixels, a first inter-stage amplifier of 12-bit 40- Msample/s pipelined ADC was designed with 0. 35 μm CMOS technology. On the basis of traditional two-stage amplifier, the cross-coupled class AB output stage and cascode compensation were adopted to improve the output vohage swing and bandwidth. Power dissipation was optimized with math tools. Circuit and layout design were completed. Simulation results show that the designed amplifier has good performance of 95 dB dc gain, ±2 V output voltage swing, 190 MHz bandwidth and 63° phase margin with feedback factor 1/4, 33 mW power dissipation and so on, which can meet the system requirements.
基金supported by the National Found for Fostering Talents of Basic Science,China(No.J0730318)the National Science and Technology Maior Project,China(Nos.J2009ZX03007-001-03,2010ZX03007-002-03)
文摘This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.
基金Project supported by the National Natural Science Foundation of China(Nos.61106024,61201176)
文摘A novel class-AB implementation of a current-mode programmable gain amplifier （CPGA） including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.
基金Project supported by the National Natural Science Foundation of China(No.61072010)the National High Technology Research&Development Program of China(No.2008AA04A 102)the Important National Science&Technology Specific Projects(No.2010ZX03007- 002-03)
文摘A novel matching method between the power amplifier （PA） and antenna of an active or semi-active RFID tag is presented. A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240 × 70 μm^2 in a 0.18μm CMOS process due to saving two on-chip integrated inductors. Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal, the PA shows a measured output power of 8 dBm at the 1 dB compression point.
