A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a hig...A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.展开更多
A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and ...A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.展开更多
A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented witho...A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.展开更多
The signal to noise ratio （SNR） of conventional sigma delta analog to digital converter （∑△ADC） reduces with input signal strength. The existing concept of adaptive quantization is applied to the design of ∑△A...The signal to noise ratio （SNR） of conventional sigma delta analog to digital converter （∑△ADC） reduces with input signal strength. The existing concept of adaptive quantization is applied to the design of ∑△ADC to improve SNR with high dynamic range. An adaptive algorithm and its circuit implementation is proposed. Because of the error due to the circuit implementation, an error self-calibration circuit is also designed. Simulation results indicate that SNR can he nearly independent of the signal strength.展开更多
This text has expounded the working principle of realizing A/D conversion that utilizes the timer within MCU and combinesthe technology of PWM. The design of hardware circuit, improved gradual approached trial arithme...This text has expounded the working principle of realizing A/D conversion that utilizes the timer within MCU and combinesthe technology of PWM. The design of hardware circuit, improved gradual approached trial arithmetic and relevant program design arediscussed in detail. And it has analyzed the resolution of A/D converter based on the technology of PWM, etc.展开更多
In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias...In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias and dose rate. Under high-dose-rate irradiation,the ADC functions well,while under low-dose-rate irradiation,the parameters of ADC change obviously at low dose level,and the damage is significant at zero bias.Combining the fringing field with the space charge model,the underlying mechanism for this response is discussed.展开更多
To solve the problem of circulating power of dual active bridge(DAB)DC-DC converter over a wide voltage conversion ratio,this paper proposes a novel synchronous PWM(S-PWM)modulation.Existence of circulating power incr...To solve the problem of circulating power of dual active bridge(DAB)DC-DC converter over a wide voltage conversion ratio,this paper proposes a novel synchronous PWM(S-PWM)modulation.Existence of circulating power increases current stress of devices and decreases efficiency,especially under light load conditions.Several modulation methods have been proposed to overcome the problem.They can reduce or eliminate either input or output side circulating power.In contrast,S-PWM not only eliminates both sides circulating power and reduces current stress,but also achieves zero-current-switching(ZCS)turn-on for all switches and ZCS turn-off for most across the full power range.No auxiliary or snubber circuits are increased.In addition,the control can be simplified so the transmitted power is related to only one variable.The S-PWM has four cases under different gain and power conditions.The detailed operation principle and modes of DAB under S-PWM are analyzed in the paper.In addition,four modulations in literature are discussed,and corresponding comparative analyses with S-PWM are given.Finally,a laboratory prototype is built to verify advantages and effectiveness of the proposed modulation.展开更多
Grid-Forming(GFM)converters are prone to fault-induced overcurrent and power angle instability during grid fault-induced voltage sags.To address this,this paper develops a multi-loop coordinated fault ridethrough(FRT)...Grid-Forming(GFM)converters are prone to fault-induced overcurrent and power angle instability during grid fault-induced voltage sags.To address this,this paper develops a multi-loop coordinated fault ridethrough(FRT)control strategy based on a power outer loop and voltage-current inner loops,aiming to enhance the stability and current-limiting capability of GFM converters during grid fault conditions.During voltage sags,the GFM converter’s voltage source behavior is maintained by dynamically adjusting the reactive power reference to provide voltage support,thereby effectively suppressing the steady-state component of the fault current.To address the active power imbalance induced by voltage sags,a dynamic active power reference correction method based on apparent power is designed to mitigate power angle oscillations and limit transient current.Moreover,an adaptive virtual impedance loop is implemented to enhance dynamic transient current-limiting performance during the fault initiation phase.This approach improves the responsiveness of the inner loop and ensures safe system operation under various fault severities.Under asymmetric fault conditions,a negative-sequence reactive current compensation strategy is incorporated to further suppress negative-sequence voltage and improve voltage symmetry.The proposed control scheme enables coordinated operation of multiple control objectives,including voltage support,current suppression,and power angle stability,across different fault scenarios.Finally,MATLAB/Simulink simulation results validate the effectiveness of the proposed strategy,showcasing its superior performance in current limiting and power angle stability,thereby significantly enhancing the system’s fault ride-through capability.展开更多
The transient synchronization stability of grid-forming converters(GFMCs)is significantly challenged under grid voltage sags.Continuous efforts have been devoted to analyzing the GFMC transient stability,with limited ...The transient synchronization stability of grid-forming converters(GFMCs)is significantly challenged under grid voltage sags.Continuous efforts have been devoted to analyzing the GFMC transient stability,with limited attention paid to the impacts of control loop dynamics.However,the complex control dynamics,especially the interactions between the active/reactive power control loops and the current saturation process(CSP),are crucial for accurately describing the transient behavior and evaluating the stability.Thus,in this study,a new large-signal GFMC model is established,considering the reactive power control(RPC)with different kinds of controllers and the CSP simultaneously.It is revealed that GFMC does not switch to the current-limited mode immediately,and the dynamics of RPC further affect the transient behavior before the current limiting significantly.Hence,the complex control dynamics can alter the mode switching point of current saturation,thereby increasing the risk of loss of synchronization(LOS).Based on the above findings,comprehensive comparisons of typical RPC controllers are presented to facilitate practical engineering applications.A unified stability enhancement method is proposed for solving the problem of LOS.Finally,experiments validate the correctness of the analysis and the effectiveness of the proposed control strategy.展开更多
In the future power-electronics-dominated power systems,grid-forming(GFM)converters have been regarded as important devices to actively establish frequency and voltage,so as to provide essential grid support.However,d...In the future power-electronics-dominated power systems,grid-forming(GFM)converters have been regarded as important devices to actively establish frequency and voltage,so as to provide essential grid support.However,due to their voltage source behavior and emulated swing dynamics,GFM converters may encounter low-frequency oscillations(LFOs)when connected to strong grids,which belongs to the self-stability problem of GFM converters.Moreover,GFM converters will also interact with grid-following(GFL)converters and thus impact the mid-frequency oscillations(MFOs)induced by phase-locked loops(PLLs).It has been preliminarily shown in the literature that GFM converters can help stabilize the PLL-induced MFOs,but currently,there is a lack of systematic design methods to coordinate the self-stability and stabilizing ability of GFM converters.This paper addresses this gap by revisiting the impedance model of a typical GFM converter and briefly analyze the oscillations caused by converters.Based on our analysis,we propose a frequency-partitioned synthesis design framework to enable dynamic virtual impedance(DVI)in GFM converters,aiming to enhance their self-stability and stabilizing ability simultaneously.Particularly,a self-stabilizing module is designed to ensure robust device-level damping,with control parameters auto-tuned using H∞methods.In parallel,a stabilizing module is introduced to stabilize GFL converters and enhance the system-level stability,which utilizes a perceive-and-optimize tuning strategy.Simulation results validate the effectiveness of the proposed synthesis DVI framework.展开更多
A multi-phase stacked interleaved buck converter(SIBC)is suitable for large-power water electrolysis applications due to its merits of high current output capability and zero output current ripple.However,the auxiliar...A multi-phase stacked interleaved buck converter(SIBC)is suitable for large-power water electrolysis applications due to its merits of high current output capability and zero output current ripple.However,the auxiliary converter used to compensate for the current ripple still has to withstand high voltage stress.This paper proposes a new multi-phase SIBC applied in the multicarrier energy system integrating electricity,heat,and hydrogen.A resistor-capacitor voltage divider is used to provide the input voltage of the auxiliary converter and as a heater for the thermal loads.Thus,the voltage stress of the auxiliary converter can be reduced at a low cost,and the size of the filter inductor can be reduced.With accurate voltage and current analysis and appropriate parameter design,the voltage stresses of both the switches and capacitors in the auxiliary converter can be further limited within an expected range.The experimental results verify the correctness of the topology,modulation,analysis,and design methods.A comparison with the conventional method is made in terms of cost,volume,and efficiency to show the advantages of the proposed method.展开更多
As key equipment in medium voltage DC(MVDC)systems,modular multilevel AC/DC and DC/DC converters(MM-AC/DC,MM-DC/DC)have drawn marvelous attractions.However,research on DC fault ride-through focuses on MM-AC/DC,and the...As key equipment in medium voltage DC(MVDC)systems,modular multilevel AC/DC and DC/DC converters(MM-AC/DC,MM-DC/DC)have drawn marvelous attractions.However,research on DC fault ride-through focuses on MM-AC/DC,and the fault current elimination for MM-DC/DC remains a research gap,which limits the wide application of the MVDC system.To fulfil this research gap,the contribution of this paper is revealing the fault current characteristics of MM-DC/DC based on half-bridge and full-bridge submodules(HBSM and FBSM)and proposing a novel MM-DC/DC based on hybrid HBSM and thyristor-diode module(TDM).By integrating TDM in the upper bridge arm of one phase and the down bridge arm of the other phase in MM-DC/DC,the MM-DC/DC achieves self-elimination of fault currents.The basic concept is using the energy at the healthy side to modulate a reverse voltage source(RVS)at the faulty side of MM-DC/DC,forcing fault current through TDM pass across zero.TDM can extinguish the resulting fault current.The parameter design and control strategy of the novel MM-DC/DC are discussed.Simulation is carried out for verification,and the results show that fault current can be eliminated within several milliseconds without causing excessive operating losses and costs.展开更多
In order to solve the problems of slow dynamic response and difficult multi-source coordination of solar electric vehicle charging stations under intermittent renewable energy,this paper proposes a hardware-algorithm ...In order to solve the problems of slow dynamic response and difficult multi-source coordination of solar electric vehicle charging stations under intermittent renewable energy,this paper proposes a hardware-algorithm co-design framework:the T-type three-level bidirectional converter(100 kHz switching frequency)based on silicon carbide(SiC)MOSFET is deeply integrated with fuzzy model predictive control(Fuzzy-MPC).At the hardware level,the switching trajectory and resonance suppression circuit(attenuation resonance peak 18 dB)are optimized,and the total loss is reduced by 23%compared with the traditional silicon-based IGBT.At the algorithm level,the adaptive parameter update mechanism and multi-objective rolling optimization are adopted,and the 5 ms level dynamic power allocation is realized by relying on edge computing.Experiments on 800 V DC microgrid(including 600 kW photovoltaic and 150 A·h energy storage)built based on MATLAB/Simulink hardware-in-the-loop(HIL)platform show that the system shortens the battery charging time from 42 to 28 min(the charging speed is increased by 33%).Through the 78%valley power utilization rate,the power purchase cost of high-priced power grids was significantly reduced,and the levelized electricity price decreased by 10.3%;Under the irradiation fluctuation,the renewable energy consumption rate increases by 10.1%,and the DC bus voltage fluctuation is stable within±10 V when the load step is±30%.The co-design provides an economically feasible and dynamically robust solution for the efficient integration of PV-ESG-EV in the smart grid.展开更多
To address the issue of abnormal energy consumption fluctuations in the converter steelmaking process,an integrated diagnostic method combining the gray wolf optimization(GWO)algorithm,support vector machine(SVM),and ...To address the issue of abnormal energy consumption fluctuations in the converter steelmaking process,an integrated diagnostic method combining the gray wolf optimization(GWO)algorithm,support vector machine(SVM),and K-means clustering was proposed.Eight input parameters—derived from molten iron conditions and external factors—were selected as feature variables.A GWO-SVM model was developed to accurately predict the energy consumption of individual heats.Based on the prediction results,the mean absolute percentage error and maximum relative error of the test set were employed as criteria to identify heats with abnormal energy usage.For these heats,the K-means clustering algorithm was used to determine benchmark values of influencing factors from similar steel grades,enabling root-cause diagnosis of excessive energy consumption.The proposed method was applied to real production data from a converter in a steel plant.The analysis reveals that heat sample No.44 exhibits abnormal energy consumption,due to gas recovery being 1430.28 kg of standard coal below the benchmark level.A secondary contributing factor is a steam recovery shortfall of 237.99 kg of standard coal.This integrated approach offers a scientifically grounded tool for energy management in converter operations and provides valuable guidance for optimizing process parameters and enhancing energy efficiency.展开更多
文摘A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.
文摘A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.
文摘A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.
文摘The signal to noise ratio （SNR） of conventional sigma delta analog to digital converter （∑△ADC） reduces with input signal strength. The existing concept of adaptive quantization is applied to the design of ∑△ADC to improve SNR with high dynamic range. An adaptive algorithm and its circuit implementation is proposed. Because of the error due to the circuit implementation, an error self-calibration circuit is also designed. Simulation results indicate that SNR can he nearly independent of the signal strength.
文摘This text has expounded the working principle of realizing A/D conversion that utilizes the timer within MCU and combinesthe technology of PWM. The design of hardware circuit, improved gradual approached trial arithmetic and relevant program design arediscussed in detail. And it has analyzed the resolution of A/D converter based on the technology of PWM, etc.
文摘In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias and dose rate. Under high-dose-rate irradiation,the ADC functions well,while under low-dose-rate irradiation,the parameters of ADC change obviously at low dose level,and the damage is significant at zero bias.Combining the fringing field with the space charge model,the underlying mechanism for this response is discussed.
文摘To solve the problem of circulating power of dual active bridge(DAB)DC-DC converter over a wide voltage conversion ratio,this paper proposes a novel synchronous PWM(S-PWM)modulation.Existence of circulating power increases current stress of devices and decreases efficiency,especially under light load conditions.Several modulation methods have been proposed to overcome the problem.They can reduce or eliminate either input or output side circulating power.In contrast,S-PWM not only eliminates both sides circulating power and reduces current stress,but also achieves zero-current-switching(ZCS)turn-on for all switches and ZCS turn-off for most across the full power range.No auxiliary or snubber circuits are increased.In addition,the control can be simplified so the transmitted power is related to only one variable.The S-PWM has four cases under different gain and power conditions.The detailed operation principle and modes of DAB under S-PWM are analyzed in the paper.In addition,four modulations in literature are discussed,and corresponding comparative analyses with S-PWM are given.Finally,a laboratory prototype is built to verify advantages and effectiveness of the proposed modulation.
文摘Grid-Forming(GFM)converters are prone to fault-induced overcurrent and power angle instability during grid fault-induced voltage sags.To address this,this paper develops a multi-loop coordinated fault ridethrough(FRT)control strategy based on a power outer loop and voltage-current inner loops,aiming to enhance the stability and current-limiting capability of GFM converters during grid fault conditions.During voltage sags,the GFM converter’s voltage source behavior is maintained by dynamically adjusting the reactive power reference to provide voltage support,thereby effectively suppressing the steady-state component of the fault current.To address the active power imbalance induced by voltage sags,a dynamic active power reference correction method based on apparent power is designed to mitigate power angle oscillations and limit transient current.Moreover,an adaptive virtual impedance loop is implemented to enhance dynamic transient current-limiting performance during the fault initiation phase.This approach improves the responsiveness of the inner loop and ensures safe system operation under various fault severities.Under asymmetric fault conditions,a negative-sequence reactive current compensation strategy is incorporated to further suppress negative-sequence voltage and improve voltage symmetry.The proposed control scheme enables coordinated operation of multiple control objectives,including voltage support,current suppression,and power angle stability,across different fault scenarios.Finally,MATLAB/Simulink simulation results validate the effectiveness of the proposed strategy,showcasing its superior performance in current limiting and power angle stability,thereby significantly enhancing the system’s fault ride-through capability.
基金supported by the National Natural Science Foundation of China under Grant 52277184 and Grant 52277183.
文摘The transient synchronization stability of grid-forming converters(GFMCs)is significantly challenged under grid voltage sags.Continuous efforts have been devoted to analyzing the GFMC transient stability,with limited attention paid to the impacts of control loop dynamics.However,the complex control dynamics,especially the interactions between the active/reactive power control loops and the current saturation process(CSP),are crucial for accurately describing the transient behavior and evaluating the stability.Thus,in this study,a new large-signal GFMC model is established,considering the reactive power control(RPC)with different kinds of controllers and the CSP simultaneously.It is revealed that GFMC does not switch to the current-limited mode immediately,and the dynamics of RPC further affect the transient behavior before the current limiting significantly.Hence,the complex control dynamics can alter the mode switching point of current saturation,thereby increasing the risk of loss of synchronization(LOS).Based on the above findings,comprehensive comparisons of typical RPC controllers are presented to facilitate practical engineering applications.A unified stability enhancement method is proposed for solving the problem of LOS.Finally,experiments validate the correctness of the analysis and the effectiveness of the proposed control strategy.
基金supported by National Natural Science Foundation of China(U24B6008,U22B6008)State Grid Zhejiang Electric Power Co.,Ltd.Science,and Technology Project(B311DS240015).
文摘In the future power-electronics-dominated power systems,grid-forming(GFM)converters have been regarded as important devices to actively establish frequency and voltage,so as to provide essential grid support.However,due to their voltage source behavior and emulated swing dynamics,GFM converters may encounter low-frequency oscillations(LFOs)when connected to strong grids,which belongs to the self-stability problem of GFM converters.Moreover,GFM converters will also interact with grid-following(GFL)converters and thus impact the mid-frequency oscillations(MFOs)induced by phase-locked loops(PLLs).It has been preliminarily shown in the literature that GFM converters can help stabilize the PLL-induced MFOs,but currently,there is a lack of systematic design methods to coordinate the self-stability and stabilizing ability of GFM converters.This paper addresses this gap by revisiting the impedance model of a typical GFM converter and briefly analyze the oscillations caused by converters.Based on our analysis,we propose a frequency-partitioned synthesis design framework to enable dynamic virtual impedance(DVI)in GFM converters,aiming to enhance their self-stability and stabilizing ability simultaneously.Particularly,a self-stabilizing module is designed to ensure robust device-level damping,with control parameters auto-tuned using H∞methods.In parallel,a stabilizing module is introduced to stabilize GFL converters and enhance the system-level stability,which utilizes a perceive-and-optimize tuning strategy.Simulation results validate the effectiveness of the proposed synthesis DVI framework.
基金supported in part by the National Natural Science Foundation of China(52077190)Cultivation Project for Basic Research and Innovation of Yanshan University(2021LGQN007)Science and Technology Project of Hebei Education Department(QN2024202).
文摘A multi-phase stacked interleaved buck converter(SIBC)is suitable for large-power water electrolysis applications due to its merits of high current output capability and zero output current ripple.However,the auxiliary converter used to compensate for the current ripple still has to withstand high voltage stress.This paper proposes a new multi-phase SIBC applied in the multicarrier energy system integrating electricity,heat,and hydrogen.A resistor-capacitor voltage divider is used to provide the input voltage of the auxiliary converter and as a heater for the thermal loads.Thus,the voltage stress of the auxiliary converter can be reduced at a low cost,and the size of the filter inductor can be reduced.With accurate voltage and current analysis and appropriate parameter design,the voltage stresses of both the switches and capacitors in the auxiliary converter can be further limited within an expected range.The experimental results verify the correctness of the topology,modulation,analysis,and design methods.A comparison with the conventional method is made in terms of cost,volume,and efficiency to show the advantages of the proposed method.
基金supported by Science and Technology Project of SGCC(5108-202218280A-2-370-XG).
文摘As key equipment in medium voltage DC(MVDC)systems,modular multilevel AC/DC and DC/DC converters(MM-AC/DC,MM-DC/DC)have drawn marvelous attractions.However,research on DC fault ride-through focuses on MM-AC/DC,and the fault current elimination for MM-DC/DC remains a research gap,which limits the wide application of the MVDC system.To fulfil this research gap,the contribution of this paper is revealing the fault current characteristics of MM-DC/DC based on half-bridge and full-bridge submodules(HBSM and FBSM)and proposing a novel MM-DC/DC based on hybrid HBSM and thyristor-diode module(TDM).By integrating TDM in the upper bridge arm of one phase and the down bridge arm of the other phase in MM-DC/DC,the MM-DC/DC achieves self-elimination of fault currents.The basic concept is using the energy at the healthy side to modulate a reverse voltage source(RVS)at the faulty side of MM-DC/DC,forcing fault current through TDM pass across zero.TDM can extinguish the resulting fault current.The parameter design and control strategy of the novel MM-DC/DC are discussed.Simulation is carried out for verification,and the results show that fault current can be eliminated within several milliseconds without causing excessive operating losses and costs.
基金Jiangsu Provincial College Student Innovation and Entrepreneurship Program(Grant No.SJCX25_2184)—“Multi-energy Complementary Optimization and Vehicle-Storage Bidirectional Interaction Technology Driven by Novel 5E Framework”(Principal Investigator:Yuan-Yuan ShiFunding Agency:Jiangsu Provincial Education Department)+3 种基金Huaian Natural Science Research Project(Grant No.HAB2024046)—“Optimal Control of Flexible Cold-Heat-Power Integrated System with Source-Grid-Load-Storage Coordination”(Principal Investigator:Jie JiFunding Agency:Huaian Science and Technology Bureau)Huaiyin Institute of TechnologyUniversity-funded Project(GrantNo.HGYK202511)—“Data-driven CooperativeOptimization Dispatch for Source-Grid-Load Systems”(Principal Investigator:Chu-Tong ZhangFunding Agency:Huaiyin Institute of Technology).
文摘In order to solve the problems of slow dynamic response and difficult multi-source coordination of solar electric vehicle charging stations under intermittent renewable energy,this paper proposes a hardware-algorithm co-design framework:the T-type three-level bidirectional converter(100 kHz switching frequency)based on silicon carbide(SiC)MOSFET is deeply integrated with fuzzy model predictive control(Fuzzy-MPC).At the hardware level,the switching trajectory and resonance suppression circuit(attenuation resonance peak 18 dB)are optimized,and the total loss is reduced by 23%compared with the traditional silicon-based IGBT.At the algorithm level,the adaptive parameter update mechanism and multi-objective rolling optimization are adopted,and the 5 ms level dynamic power allocation is realized by relying on edge computing.Experiments on 800 V DC microgrid(including 600 kW photovoltaic and 150 A·h energy storage)built based on MATLAB/Simulink hardware-in-the-loop(HIL)platform show that the system shortens the battery charging time from 42 to 28 min(the charging speed is increased by 33%).Through the 78%valley power utilization rate,the power purchase cost of high-priced power grids was significantly reduced,and the levelized electricity price decreased by 10.3%;Under the irradiation fluctuation,the renewable energy consumption rate increases by 10.1%,and the DC bus voltage fluctuation is stable within±10 V when the load step is±30%.The co-design provides an economically feasible and dynamically robust solution for the efficient integration of PV-ESG-EV in the smart grid.
基金support from the National Key R&D Program of China(Grant No.2020YFB1711100).
文摘To address the issue of abnormal energy consumption fluctuations in the converter steelmaking process,an integrated diagnostic method combining the gray wolf optimization(GWO)algorithm,support vector machine(SVM),and K-means clustering was proposed.Eight input parameters—derived from molten iron conditions and external factors—were selected as feature variables.A GWO-SVM model was developed to accurately predict the energy consumption of individual heats.Based on the prediction results,the mean absolute percentage error and maximum relative error of the test set were employed as criteria to identify heats with abnormal energy usage.For these heats,the K-means clustering algorithm was used to determine benchmark values of influencing factors from similar steel grades,enabling root-cause diagnosis of excessive energy consumption.The proposed method was applied to real production data from a converter in a steel plant.The analysis reveals that heat sample No.44 exhibits abnormal energy consumption,due to gas recovery being 1430.28 kg of standard coal below the benchmark level.A secondary contributing factor is a steam recovery shortfall of 237.99 kg of standard coal.This integrated approach offers a scientifically grounded tool for energy management in converter operations and provides valuable guidance for optimizing process parameters and enhancing energy efficiency.
