A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a hig...A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.展开更多
A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and ...A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.展开更多
A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented witho...A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.展开更多
The signal to noise ratio （SNR） of conventional sigma delta analog to digital converter （∑△ADC） reduces with input signal strength. The existing concept of adaptive quantization is applied to the design of ∑△A...The signal to noise ratio （SNR） of conventional sigma delta analog to digital converter （∑△ADC） reduces with input signal strength. The existing concept of adaptive quantization is applied to the design of ∑△ADC to improve SNR with high dynamic range. An adaptive algorithm and its circuit implementation is proposed. Because of the error due to the circuit implementation, an error self-calibration circuit is also designed. Simulation results indicate that SNR can he nearly independent of the signal strength.展开更多
This text has expounded the working principle of realizing A/D conversion that utilizes the timer within MCU and combinesthe technology of PWM. The design of hardware circuit, improved gradual approached trial arithme...This text has expounded the working principle of realizing A/D conversion that utilizes the timer within MCU and combinesthe technology of PWM. The design of hardware circuit, improved gradual approached trial arithmetic and relevant program design arediscussed in detail. And it has analyzed the resolution of A/D converter based on the technology of PWM, etc.展开更多
In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias...In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias and dose rate. Under high-dose-rate irradiation,the ADC functions well,while under low-dose-rate irradiation,the parameters of ADC change obviously at low dose level,and the damage is significant at zero bias.Combining the fringing field with the space charge model,the underlying mechanism for this response is discussed.展开更多
Grid-Forming(GFM)converters are prone to fault-induced overcurrent and power angle instability during grid fault-induced voltage sags.To address this,this paper develops a multi-loop coordinated fault ridethrough(FRT)...Grid-Forming(GFM)converters are prone to fault-induced overcurrent and power angle instability during grid fault-induced voltage sags.To address this,this paper develops a multi-loop coordinated fault ridethrough(FRT)control strategy based on a power outer loop and voltage-current inner loops,aiming to enhance the stability and current-limiting capability of GFM converters during grid fault conditions.During voltage sags,the GFM converter’s voltage source behavior is maintained by dynamically adjusting the reactive power reference to provide voltage support,thereby effectively suppressing the steady-state component of the fault current.To address the active power imbalance induced by voltage sags,a dynamic active power reference correction method based on apparent power is designed to mitigate power angle oscillations and limit transient current.Moreover,an adaptive virtual impedance loop is implemented to enhance dynamic transient current-limiting performance during the fault initiation phase.This approach improves the responsiveness of the inner loop and ensures safe system operation under various fault severities.Under asymmetric fault conditions,a negative-sequence reactive current compensation strategy is incorporated to further suppress negative-sequence voltage and improve voltage symmetry.The proposed control scheme enables coordinated operation of multiple control objectives,including voltage support,current suppression,and power angle stability,across different fault scenarios.Finally,MATLAB/Simulink simulation results validate the effectiveness of the proposed strategy,showcasing its superior performance in current limiting and power angle stability,thereby significantly enhancing the system’s fault ride-through capability.展开更多
目的研究昆明地区RhD初筛阴性献血者RHD基因的多态性及其分子机制,为建立区域性献血者RHD基因数据库提供数据支持。方法选择昆明地区2023年11月-2024年8月初筛RhD阴性标本218例,采用间接抗球蛋白试验法(IAT)进行RhD阴性确认,采用盐水试...目的研究昆明地区RhD初筛阴性献血者RHD基因的多态性及其分子机制,为建立区域性献血者RHD基因数据库提供数据支持。方法选择昆明地区2023年11月-2024年8月初筛RhD阴性标本218例,采用间接抗球蛋白试验法(IAT)进行RhD阴性确认,采用盐水试管法进行RhCE表型鉴定。提取全血基因组DNA,采用PCR-SSP法/SSP荧光PCR染料法进行RHD基因分型,对无法确定基因型的标本进行RHD基因1~10外显子Sanger测序分析。结果检出RhD真阴性表型179例(82.11%),其中RHD*01N.01(RHD全缺失)型154例(86.03%),表型以ccee为主(87.01%);携带非功能性RHD等位基因25例(13.97%),包括RHD*01N.0320例、RHD*01N.163例、RHD*01N.051例、RHD*01N.591例,表型以Ccee为主(64%)。检出D变异型39例(15.89%),其中RHD*DEL1(c.1227G>A)型34例,表型均为C抗原阳性(Ccee 27例,CCee 7例);弱D/部分D型4例,包括RHD*DVI.32例、RHD*weak D type 711例、RHD*weak D type1081例;另检出1例RHD*01/RHD*01N.01,基因型与血清学表型结果不一致。RHD*01N.01女性献血者不规则抗体(主要为抗-D)阳性率9.84%。结论昆明地区RhD初筛阴性献血者RHD基因多态性显著,RhD真阴性比例高于国内部分地区,D变异型以“亚洲型”DEL为主,比例低于国内部分地区。研究结果为本地区RhD阴性和D变异型个体精准输血提供了理论和数据支持。展开更多
目的:探究3D全腹腔镜根治术治疗Ⅲ期远端胃癌的疗效及安全性。方法:收集2021年2月至2024年2月收治的Ⅲ期远端胃癌患者的临床资料。将接受腹腔镜辅助远端胃癌根治术的患者纳入对照组,将接受3D全腹腔镜辅助远端胃癌根治术的患者纳入观察组...目的:探究3D全腹腔镜根治术治疗Ⅲ期远端胃癌的疗效及安全性。方法:收集2021年2月至2024年2月收治的Ⅲ期远端胃癌患者的临床资料。将接受腹腔镜辅助远端胃癌根治术的患者纳入对照组,将接受3D全腹腔镜辅助远端胃癌根治术的患者纳入观察组,采用倾向性评分匹配法以最邻近匹配原则1∶1进行匹配,最终两组各纳入60例。比较两组手术情况、术后恢复情况、术后疼痛程度评分(VAS)、围手术期应激反应指标、胃肠功能指标及并发症发生情况。结果:与对照组相比,观察组切口长度、消化道重建时间、术后首次排气时间、自主下床活动时间及住院时间更短,使用镇痛药物患者比例更低,切口美容评分更高,术后并发症发生率更低(P<0.05)。术后8、24、48、72 h两组VAS均低于治疗前,且观察组低于对照组(P<0.05)。观察组术后24、72 h ACTH、PGE2升高幅度和MTL、GAS降低幅度均小于对照组(P<0.05)。结论:3D全腹腔镜根治术治疗Ⅲ期远端胃癌创伤小、术后并发症少,有利于胃肠功能早期恢复,且具有切口美观的优势。展开更多
文摘A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.
文摘A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.
文摘A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.
文摘The signal to noise ratio （SNR） of conventional sigma delta analog to digital converter （∑△ADC） reduces with input signal strength. The existing concept of adaptive quantization is applied to the design of ∑△ADC to improve SNR with high dynamic range. An adaptive algorithm and its circuit implementation is proposed. Because of the error due to the circuit implementation, an error self-calibration circuit is also designed. Simulation results indicate that SNR can he nearly independent of the signal strength.
文摘This text has expounded the working principle of realizing A/D conversion that utilizes the timer within MCU and combinesthe technology of PWM. The design of hardware circuit, improved gradual approached trial arithmetic and relevant program design arediscussed in detail. And it has analyzed the resolution of A/D converter based on the technology of PWM, etc.
文摘In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias and dose rate. Under high-dose-rate irradiation,the ADC functions well,while under low-dose-rate irradiation,the parameters of ADC change obviously at low dose level,and the damage is significant at zero bias.Combining the fringing field with the space charge model,the underlying mechanism for this response is discussed.
文摘Grid-Forming(GFM)converters are prone to fault-induced overcurrent and power angle instability during grid fault-induced voltage sags.To address this,this paper develops a multi-loop coordinated fault ridethrough(FRT)control strategy based on a power outer loop and voltage-current inner loops,aiming to enhance the stability and current-limiting capability of GFM converters during grid fault conditions.During voltage sags,the GFM converter’s voltage source behavior is maintained by dynamically adjusting the reactive power reference to provide voltage support,thereby effectively suppressing the steady-state component of the fault current.To address the active power imbalance induced by voltage sags,a dynamic active power reference correction method based on apparent power is designed to mitigate power angle oscillations and limit transient current.Moreover,an adaptive virtual impedance loop is implemented to enhance dynamic transient current-limiting performance during the fault initiation phase.This approach improves the responsiveness of the inner loop and ensures safe system operation under various fault severities.Under asymmetric fault conditions,a negative-sequence reactive current compensation strategy is incorporated to further suppress negative-sequence voltage and improve voltage symmetry.The proposed control scheme enables coordinated operation of multiple control objectives,including voltage support,current suppression,and power angle stability,across different fault scenarios.Finally,MATLAB/Simulink simulation results validate the effectiveness of the proposed strategy,showcasing its superior performance in current limiting and power angle stability,thereby significantly enhancing the system’s fault ride-through capability.
文摘目的研究昆明地区RhD初筛阴性献血者RHD基因的多态性及其分子机制,为建立区域性献血者RHD基因数据库提供数据支持。方法选择昆明地区2023年11月-2024年8月初筛RhD阴性标本218例,采用间接抗球蛋白试验法(IAT)进行RhD阴性确认,采用盐水试管法进行RhCE表型鉴定。提取全血基因组DNA,采用PCR-SSP法/SSP荧光PCR染料法进行RHD基因分型,对无法确定基因型的标本进行RHD基因1~10外显子Sanger测序分析。结果检出RhD真阴性表型179例(82.11%),其中RHD*01N.01(RHD全缺失)型154例(86.03%),表型以ccee为主(87.01%);携带非功能性RHD等位基因25例(13.97%),包括RHD*01N.0320例、RHD*01N.163例、RHD*01N.051例、RHD*01N.591例,表型以Ccee为主(64%)。检出D变异型39例(15.89%),其中RHD*DEL1(c.1227G>A)型34例,表型均为C抗原阳性(Ccee 27例,CCee 7例);弱D/部分D型4例,包括RHD*DVI.32例、RHD*weak D type 711例、RHD*weak D type1081例;另检出1例RHD*01/RHD*01N.01,基因型与血清学表型结果不一致。RHD*01N.01女性献血者不规则抗体(主要为抗-D)阳性率9.84%。结论昆明地区RhD初筛阴性献血者RHD基因多态性显著,RhD真阴性比例高于国内部分地区,D变异型以“亚洲型”DEL为主,比例低于国内部分地区。研究结果为本地区RhD阴性和D变异型个体精准输血提供了理论和数据支持。
文摘目的:探究3D全腹腔镜根治术治疗Ⅲ期远端胃癌的疗效及安全性。方法:收集2021年2月至2024年2月收治的Ⅲ期远端胃癌患者的临床资料。将接受腹腔镜辅助远端胃癌根治术的患者纳入对照组,将接受3D全腹腔镜辅助远端胃癌根治术的患者纳入观察组,采用倾向性评分匹配法以最邻近匹配原则1∶1进行匹配,最终两组各纳入60例。比较两组手术情况、术后恢复情况、术后疼痛程度评分(VAS)、围手术期应激反应指标、胃肠功能指标及并发症发生情况。结果:与对照组相比,观察组切口长度、消化道重建时间、术后首次排气时间、自主下床活动时间及住院时间更短,使用镇痛药物患者比例更低,切口美容评分更高,术后并发症发生率更低(P<0.05)。术后8、24、48、72 h两组VAS均低于治疗前,且观察组低于对照组(P<0.05)。观察组术后24、72 h ACTH、PGE2升高幅度和MTL、GAS降低幅度均小于对照组(P<0.05)。结论:3D全腹腔镜根治术治疗Ⅲ期远端胃癌创伤小、术后并发症少,有利于胃肠功能早期恢复,且具有切口美观的优势。
