This paper analyzes cache coherency mechanism from the view of system. It firstly discusses caehe-memory hierarchy of Pentium Ⅲ SMP system, including memory area distribution, cache attributes control and bus transac...This paper analyzes cache coherency mechanism from the view of system. It firstly discusses caehe-memory hierarchy of Pentium Ⅲ SMP system, including memory area distribution, cache attributes control and bus transaction. Secondly it analyzes hardware snoopy mechanism of P6 bus and MESI state transitions adopted by Pentium Ⅲ. Based on these, it focuses on how muhiprocessors and the P6 bus cooperate to ensure cache coherency of the whole system, and gives the key of cache coherency design.展开更多
Dynamic Reactive Power Optimization(DRPO) is a large-scale, multi-period, and strongly coupled nonlinear mixed-integer programming problem that is difficult to solve directly. First, to handle discrete variables and s...Dynamic Reactive Power Optimization(DRPO) is a large-scale, multi-period, and strongly coupled nonlinear mixed-integer programming problem that is difficult to solve directly. First, to handle discrete variables and switching operation constraints, DRPO is formulated as a nonlinear constrained two-objective optimization problem in this paper. The first objective is to minimize the real power loss and the Total Voltage Deviations(TVDs), and the second objective is to minimize incremental system loss. Then a Filter Collaborative State Transition Algorithm(FCSTA) is presented for solving DRPO problems. Two populations corresponding to two different objectives are employed. Moreover, the filter technique is utilized to deal with constraints. Finally, the effectiveness of the proposed method is demonstrated through the results obtained for a 24-hour test on Ward & Hale 6 bus, IEEE 14 bus, and IEEE 30 bus test power systems. To substantiate the effectiveness of the proposed algorithms, the obtained results are compared with different approaches in the literature.展开更多
The 2006 light bus market was highlighted by recovery, diesel engine and dark horse. The growth rate of the sales achieved a 10 percent up year on year.
文摘This paper analyzes cache coherency mechanism from the view of system. It firstly discusses caehe-memory hierarchy of Pentium Ⅲ SMP system, including memory area distribution, cache attributes control and bus transaction. Secondly it analyzes hardware snoopy mechanism of P6 bus and MESI state transitions adopted by Pentium Ⅲ. Based on these, it focuses on how muhiprocessors and the P6 bus cooperate to ensure cache coherency of the whole system, and gives the key of cache coherency design.
基金supported by the National Natural Science Foundation of China(Nos.51767022 and 51575469)
文摘Dynamic Reactive Power Optimization(DRPO) is a large-scale, multi-period, and strongly coupled nonlinear mixed-integer programming problem that is difficult to solve directly. First, to handle discrete variables and switching operation constraints, DRPO is formulated as a nonlinear constrained two-objective optimization problem in this paper. The first objective is to minimize the real power loss and the Total Voltage Deviations(TVDs), and the second objective is to minimize incremental system loss. Then a Filter Collaborative State Transition Algorithm(FCSTA) is presented for solving DRPO problems. Two populations corresponding to two different objectives are employed. Moreover, the filter technique is utilized to deal with constraints. Finally, the effectiveness of the proposed method is demonstrated through the results obtained for a 24-hour test on Ward & Hale 6 bus, IEEE 14 bus, and IEEE 30 bus test power systems. To substantiate the effectiveness of the proposed algorithms, the obtained results are compared with different approaches in the literature.
文摘The 2006 light bus market was highlighted by recovery, diesel engine and dark horse. The growth rate of the sales achieved a 10 percent up year on year.
