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Optimizing 55 nm split-gate memory for compute-in-memory:a focus on floating-gate engineering
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作者 Wanyi Ling Ranran Liu +12 位作者 Kun Ren Dianyu Qi Yongyu Wu Guangji Li Miao Zhou Qingshuang Xu Zhenghui Xia Xuan Li Dertsyr Fan Ichun Chuang Tzung Wen Cheng Chenming Tsai Dawei Gao 《Journal of Semiconductors》 2026年第3期46-53,共8页
The escalating need for high-performance artificial intelligence(AI)computing intensifies the"memory bottleneck"of the von Neumann architecture,prompting extensive exploration of computation-in-memory(CIM)so... The escalating need for high-performance artificial intelligence(AI)computing intensifies the"memory bottleneck"of the von Neumann architecture,prompting extensive exploration of computation-in-memory(CIM)solutions.This study is cen-tered on the optimization of a high-efficiency,low-power"L"-shaped split-gate floating-gate(FG)memory for CIM applications.Fabricated on a 55 nm CMOS platform,the memory devices were systematically investigated through wafer acceptance test(WAT),Sentaurus™simulations and comprehensive evaluations with the DNN+NeuroSim Framework V2.0.Among devices with diverse FG lengths,the 95-nm FG variant exhibits outstanding performance:it achieves a 5.35 V memory window,reaches a maximum conductance of 16.7μS with excellent linearity under the varying voltage and width pulse scheme(VWPS),real-izes 32-state multi-level storage,and attains a 92%training accuracy on the CIFAR-10 dataset using the VGG8 neural network. 展开更多
关键词 split-gate floating-gate 55 nm technology node computation-in-memory
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