Compression and encryption are widely used in network traffic in order to improve efficiency and security of some systems.We propose a scheme to concatenate both functions and run them in a paralle pipelined fashion,d...Compression and encryption are widely used in network traffic in order to improve efficiency and security of some systems.We propose a scheme to concatenate both functions and run them in a paralle pipelined fashion,demonstrating both a hardware and a software implementation.With minor modifications to the hardware accelerators,latency can be reduced to half.Furthermore,we also propose a seminal and more efficient scheme,where we integrate the technology of encryption into the compression algorithm.Our new integrated optimization scheme reaches an increase of 1.6X by using parallel software scheme However,the security level of our new scheme is not desirable compare with previous ones.Fortunately,we prove that this does not affect the application of our schemes.展开更多
The security of CPU smart cards, which are widely used throughout China, is currently being threatened by side-channel analysis. Typical countermeasures to side-channel analysis involve adding noise and filtering the ...The security of CPU smart cards, which are widely used throughout China, is currently being threatened by side-channel analysis. Typical countermeasures to side-channel analysis involve adding noise and filtering the power consumption signal. In this paper, we integrate appropriate preprocessing methods with an improved attack strategy to generate a key recovery solution to the shortcomings of these countermeasures. Our proposed attack strategy improves the attack result by combining information leaked from two adjacent clock cycles. Using our laboratory-based power analysis system, we verified the proposed key recovery solution by performing a successful correlation power analysis on a Triple Data Encryption Standard （3DES） hardware module in a real-life 32-bit CPU smart card. All 112 key bits of the 3DES were recovered with about 80 000 power traces.展开更多
基金partially supported by National Natural Science Foundation of China(No. 61202475,61572294,61502218)Outstanding Young Scientists Foundation Grant of Shandong Province(No.BS2014DX016)+3 种基金Nature Science Foundation of Shandong Province (No.ZR2012FQ029)Ph.D.Programs Foundation of Ludong University(No.LY2015033)Fujian Provincial Key Laboratory of Network Security and Cryptology Research Fund(Fujian Normal University)(No.15004)the Priority Academic Program Development of Jiangsu Higer Education Institutions,Jiangsu Collaborative Innovation Center on Atmospheric Environment and Equipment Technology
文摘Compression and encryption are widely used in network traffic in order to improve efficiency and security of some systems.We propose a scheme to concatenate both functions and run them in a paralle pipelined fashion,demonstrating both a hardware and a software implementation.With minor modifications to the hardware accelerators,latency can be reduced to half.Furthermore,we also propose a seminal and more efficient scheme,where we integrate the technology of encryption into the compression algorithm.Our new integrated optimization scheme reaches an increase of 1.6X by using parallel software scheme However,the security level of our new scheme is not desirable compare with previous ones.Fortunately,we prove that this does not affect the application of our schemes.
基金supported by the Major Program“Core of Electronic DevicesHigh-End General Chips+1 种基金and Basis of Software Products”of the Ministry of Industry and Information Technology of China(No.2014ZX01032205)the Key Technologies Research and Development Program of the Twelfth Five-Year Plan of China(No.MMJJ201401009)
文摘The security of CPU smart cards, which are widely used throughout China, is currently being threatened by side-channel analysis. Typical countermeasures to side-channel analysis involve adding noise and filtering the power consumption signal. In this paper, we integrate appropriate preprocessing methods with an improved attack strategy to generate a key recovery solution to the shortcomings of these countermeasures. Our proposed attack strategy improves the attack result by combining information leaked from two adjacent clock cycles. Using our laboratory-based power analysis system, we verified the proposed key recovery solution by performing a successful correlation power analysis on a Triple Data Encryption Standard （3DES） hardware module in a real-life 32-bit CPU smart card. All 112 key bits of the 3DES were recovered with about 80 000 power traces.
