For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS...For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pellieoni structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.展开更多
Further improvement of storage density is a key challenge for the application of phase-change memory(PCM)in storage-class memory.However,for PCM,storage density improvements include feature size scaling down and multi...Further improvement of storage density is a key challenge for the application of phase-change memory(PCM)in storage-class memory.However,for PCM,storage density improvements include feature size scaling down and multilevel cell(MLC)operation,potentially causing thermal crosstalk issues and phase separation issues,respectively.To address these challenges,we propose a high-aspect-ratio(25:1)lateral nanowire(NW)PCM device with conventional chalcogenide Ge_(2)Sb_(2)Te_(5)(GST-225)to realize stable MLC operations,i.e.,low intra-and inter-cell variability and low resistance drift(coefficient=0.009).The improved MLC performance is attributed to the high aspect ratio,which enables precise control of the amorphous region because of sidewall confinement,as confirmed by transmission electron microscopy analysis.In summary,the NW devices provide guidance for the design of future high-aspect-ratio threedimensional PCM devices with MLC capability.展开更多
文摘For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pellieoni structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.
基金supported by the National Natural Science Foundation of China(62174065)the Key Research and Development Plan of Hubei Province(2020BAB007)+1 种基金Hubei Provincial Natural Science Foundation(2021CFA038)the support from Hubei Key Laboratory of Advanced Memories&Hubei Engineering Research Center on Microelectronics。
文摘Further improvement of storage density is a key challenge for the application of phase-change memory(PCM)in storage-class memory.However,for PCM,storage density improvements include feature size scaling down and multilevel cell(MLC)operation,potentially causing thermal crosstalk issues and phase separation issues,respectively.To address these challenges,we propose a high-aspect-ratio(25:1)lateral nanowire(NW)PCM device with conventional chalcogenide Ge_(2)Sb_(2)Te_(5)(GST-225)to realize stable MLC operations,i.e.,low intra-and inter-cell variability and low resistance drift(coefficient=0.009).The improved MLC performance is attributed to the high aspect ratio,which enables precise control of the amorphous region because of sidewall confinement,as confirmed by transmission electron microscopy analysis.In summary,the NW devices provide guidance for the design of future high-aspect-ratio threedimensional PCM devices with MLC capability.
