Flexible electronics face critical challenges in achieving monolithic three-dimensional(3D)integration,including material compatibility,structural stability,and scalable fabrication methods.Inspired by the tactile sen...Flexible electronics face critical challenges in achieving monolithic three-dimensional(3D)integration,including material compatibility,structural stability,and scalable fabrication methods.Inspired by the tactile sensing mechanism of the human skin,we have developed a flexible monolithic 3D-integrated tactile sensing system based on a holey MXene paste,where each vertical one-body unit simultaneously functions as a microsupercapacitor and pressure sensor.The in-plane mesopores of MXene significantly improve ion accessibility,mitigate the self-stacking of nanosheets,and allow the holey MXene to multifunctionally act as a sensing material,an active electrode,and a conductive interconnect,thus drastically reducing the interface mismatch and enhancing the mechanical robustness.Furthermore,we fabricate a large-scale device using a blade-coating and stamping method,which demonstrates excellent mechanical flexibility,low-power consumption,rapid response,and stable long-term operation.As a proof-of-concept application,we integrate our sensing array into a smart access control system,leveraging deep learning to accurately identify users based on their unique pressing behaviors.This study provides a promising approach for designing highly integrated,intelligent,and flexible electronic systems for advanced human-computer interactions and personalized electronics.展开更多
Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the ...Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the evolution of M3D integration from traditional bulk semiconductors to low-dimensional materials like two-dimensioanl(2D)transition metal dichalcogenides(TMDCs)and carbon nanotubes(CNTs).Key applications include logic circuits,static random access memory(SRAM),resistive random access memory(RRAM),sensors,optoelectronics,and artificial intelligence(AI)processing.M3D integration enhances device performance by reducing footprint,improving power efficiency,and alleviating the von Neumann bottleneck.The integration of 2D materials in M3D structures demonstrates significant advancements in terms of scalability,energy efficiency,and functional diversity.Challenges in manufacturing and scaling are discussed,along with prospects for future research directions.Overall,the M3D integration with low-dimensional materials presents a promising pathway for the development of next-generation electronic devices and systems.展开更多
With the development of 3D integration technology, microsystems with vertical interconnects are attracting attention from researchers and industry applications. Basic elements of integrated passive devices （IPDs）, i...With the development of 3D integration technology, microsystems with vertical interconnects are attracting attention from researchers and industry applications. Basic elements of integrated passive devices （IPDs）, including inductors, capacitors, and resistors, could dramatically save the tbotprint of the system, optimize the form factor, and improve the performance of radio frequency （RF） systems. In this paper, IPDs using thin film built-up technology are introduced, and the design and characterization of coplanar waveguides （CPWs）, inductors, and capacitors are presented.展开更多
Polymer insulating through-silicon-vias （TSVs） is an attractive approach for high-performance 3D integration systems. To further demonstrate the polymer insulating TSVs, this paper investigates the thermal stability...Polymer insulating through-silicon-vias （TSVs） is an attractive approach for high-performance 3D integration systems. To further demonstrate the polymer insulating TSVs, this paper investigates the thermal stability by measuring the leakage current under bias-temperature condition, studies the thermal stress characteristics with Finite Element Analysis （FEA）, and tries to improve the thermal mechanical reliability of high-density TSVs array by optimizing the geometry parameters of pitch, liner and redistribution layer （RDL）. The electrical measurements show the polymer insulating TSVs can maintain good insulation capability （less than 2x 10TM A） under challenging bias-temperature conditions of 20 V and 200~C, despite the leakage degra- dation observation. The FEA results show that the thermal stress is significantly reduced at the sidewall, but highly concen- trates at the surface, which is the potential location of mechanical failure. And, the analysis results indicate that the polymer insulating TSVs （diameter of 10 μm, depth of 50 μm） array with a pitch of 20 μm, liner thickness of 1 μm and RDL radius of 9 μm has an optimized thermal-mechanical reliability for application.展开更多
This study investigates the low-velocity impact and post-impact flexural properties of 3D integrated woven spacer composites,focusing on their orthotropic behavior when tested along two principal directions,i.e.,warp(...This study investigates the low-velocity impact and post-impact flexural properties of 3D integrated woven spacer composites,focusing on their orthotropic behavior when tested along two principal directions,i.e.,warp(X-type)and weft(Y-type)directions.The same composite material was tested in these orientations to evaluate the differences in impact resistance and residual bending strength.Specimens were fabricated via vacuum-assisted molding and tested at 2,3,5,and 7 J impact energies using an Instron Ceast 9350 drop-weight impact testing machine,in accordance with ASTM D7136.Post-impact flexural tests were performed using a four-point bending method in accordance with ASTM D7264.The absorbed energy increased from 1.97 to 6.98 J,and the panel damage area ranged from 121 to 361 mm^(2) as impact energy roses.Specimens tested in the weft direction(Y-type)showed greater residual strength(up to 15.83 N)and displacement(up to 0.538 mm)than those tested in the warp direction(X-type).Ultrasonic C-scan imaging revealed localized matrix cracking and fiber failure damage patterns.Results emphasize the directional differences in impact resistance and residual bending properties,highlighting the importance of material orientation in structural applications.This study provides a foundation for utilizing 3D woven spacer composites in lightweight,damage-tolerant structural components.展开更多
As silicon-based transistors face fundamental scaling limits,the search for breakthrough alternatives has led to innovations in 3D architectures,heterogeneous integration,and sub-3 nm semiconductor body thicknesses.Ho...As silicon-based transistors face fundamental scaling limits,the search for breakthrough alternatives has led to innovations in 3D architectures,heterogeneous integration,and sub-3 nm semiconductor body thicknesses.However,the true effectiveness of these advancements lies in the seamless integration of alternative semiconductors tailored for next-generation transistors.In this review,we highlight key advances that enhance both scalability and switching performance by leveraging emerging semiconductor materials.Among the most promising candidates are 2D van der Waals semiconductors,Mott insulators,and amorphous oxide semiconductors,which offer not only unique electrical properties but also low-power operation and high carrier mobility.Additionally,we explore the synergistic interactions between these novel semiconductors and advanced gate dielectrics,including high-K materials,ferroelectrics,and atomically thin hexagonal boron nitride layers.Beyond introducing these novel material configurations,we address critical challenges such as leakage current and long-term device reliability,which become increasingly crucial as transistors scale down to atomic dimensions.Through concrete examples showcasing the potential of these materials in transistors,we provide key insights into overcoming fundamental obstacles—such as device reliability,scaling down limitations,and extended applications in artificial intelligence—ultimately paving the way for the development of future transistor technologies.展开更多
A 3D fan-out packaging method for the integration of 5G communication RF microsystem and antenna is studied.First of all,through the double-sided wiring technology on the glass wafer,the fabrication of 5G antenna arra...A 3D fan-out packaging method for the integration of 5G communication RF microsystem and antenna is studied.First of all,through the double-sided wiring technology on the glass wafer,the fabrication of 5G antenna array is realized.Then the low power devices such as through silicon via(TSV)transfer chips,filters and antenna tuners are flip-welded on the glass wafer,and the glass wafer is reformed into a wafer permanently bonded with glass and resin by the injection molding process with resin material.Finally,the thinning resin surface leaks out of the TSV transfer chip,the rewiring is carried out on the resin surface,and then the power amplifier,low-noise amplifier,power management and other devices are flip-welded on the resin wafer surface.A ball grid array(BGA)is implanted to form the final package.The loss of the RF transmission line is measured by using the RF millimeter wave probe table.The results show that the RF transmission loss from the chip end to the antenna end in the fan-out package is very small,and it is only 0.26 dB/mm when working in 60 GHz.A slot coupling antenna is designed on the glass wafer.The antenna can operate at 60 GHz and the maximum gain can reach 6 dB within the working bandwidth.This demonstration successfully provides a feasible solution for the 3D fan-out integration of RF microsystem and antenna in 5G communications.展开更多
Some key issues in supporting collaborative design in product data management（PDM ） system and 3D computer aided design（CAD） system integrated environment are analyzed. The general architecture of the integrated e...Some key issues in supporting collaborative design in product data management（PDM ） system and 3D computer aided design（CAD） system integrated environment are analyzed. The general architecture of the integrated environment is divided into five tiers and employs the transparently integrated mode, with the mode, function calling and information exchanging among independent PDM and CAD processes are carried out via message translation /parse approach. Product layout feature（PLF ） model definition is presented, PLF model is used to represent design intention at the preliminary design phase. The collaborative design methodology employing the PLF model in PDM/3D CAD integrated environment is analyzed. The design methodology can speed up the design process, reduce the investment and improve the product quality.展开更多
Additive manufacturing(AM)is a free-form technology that shows great potential in the integrated creation of three-dimensional(3D)electronics.However,the fabrication of 3D conformal circuits that fulfill the requireme...Additive manufacturing(AM)is a free-form technology that shows great potential in the integrated creation of three-dimensional(3D)electronics.However,the fabrication of 3D conformal circuits that fulfill the requirements of high service temperature,high conductivity and high resolution remains a challenge.In this paper,a hybrid AM method combining the fused deposition modeling(FDM)and hydrophobic treatment assisted laser activation metallization(LAM)was proposed for manufacturing the polyetheretherketone(PEEK)-based 3D electronics,by which the conformal copper patterns were deposited on the 3D-printed PEEK parts,and the adhesion between them reached the 5B high level.Moreover,the 3D components could support the thermal cycling test from-55℃ to 125℃ for more than 100 cycles.Particularly,the application of a hydrophobic coating on the FDM-printed PEEK before LAM can promote an ideal catalytic selectivity on its surface,not affected by the inevitable printing borders and pores in the FDM-printed parts,then making the resolution of the electroless plated copper lines improved significantly.In consequence,Cu lines with width and spacing of only60μm and 100μm were obtained on both as-printed and after-polished PEEK substrates.Finally,the potential of this technique to fabricate 3D conformal electronics was demonstrated.展开更多
In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is bu...In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.展开更多
FeS_(2)cathode is promising for all-solid-state lithium batteries due to its ultra-high capacity,low cost,and environmental friendliness.However,the poor performances,induced by limited electrode-electrolyte interface...FeS_(2)cathode is promising for all-solid-state lithium batteries due to its ultra-high capacity,low cost,and environmental friendliness.However,the poor performances,induced by limited electrode-electrolyte interface,severe volume expansion,and polysulfide shuttle,hinder the application of FeS_(2)in all-solid-state lithium batteries.Herein,an integrated 3D FeS_(2)electrode with full infiltration of Li6PS5Cl sulfide electrolytes is designed to address these challenges.Such a 3D integrated design not only achieves intimate and maximized interfacial contact between electrode and sulfide electrolytes,but also effectively buffers the inner volume change of FeS_(2)and completely eliminates the polysulfide shuttle through direct solid-solid conversion of Li2S/S.Besides,the vertical 3D arrays guarantee direct electron transport channels and horizontally shortened ion diffusion paths,endowing the integrated electrode with a remarkably reduced interfacial impedance and enhanced reaction kinetics.Benefiting from these synergies,the integrated all-solid-state lithium battery exhibits the largest reversible capacity(667 mAh g^(-1)),best rate performance,and highest capacity retention of 82%over 500 cycles at 0.1 C compared to both a liquid battery and non-integrated all-solid-state lithium battery.The cycling performance is among the best reported for FeS_(2)-based all-solid-state lithium batteries.This work presents an innovative synergistic strategy for designing long-cycling high-energy all-solid-state lithium batteries,which can be readily applied to other battery systems,such as lithium-sulfur batteries.展开更多
Since 3D printed hard materials could match the shape of bone,cell survival and fate determination towards osteoblasts in such materials have become a popular research target.In this study,a scaffold of hardmaterial f...Since 3D printed hard materials could match the shape of bone,cell survival and fate determination towards osteoblasts in such materials have become a popular research target.In this study,a scaffold of hardmaterial for 3D fabrication was designed to regulate developmental signal(Notch)transduction guiding osteoblast differentiation.We established a polycaprolactone(PCL)and cell-integrated 3D printing system(PCI3D)to reciprocally print the beams of PCL and cell-laden hydrogel for a module.This PCI3D module holds good cell viability of over 87%,whereas cells show about sixfold proliferation in a 7-day culture.The osteocytic MLO-Y4 was engineered to overexpress Notch ligand Dll4,making up 25%after mixing with 75%stromal cells in the PCI3D module.Osteocytic Dll4,unlike other delta-like family members such as Dll1 or Dll3,promotes osteoblast differentiation and themineralization of primary mouse and a cell line of bone marrow stromal cells when cultured in a PCI3D module for up to 28 days.Mechanistically,osteocytic Dll4 could not promote osteogenic differentiation of the primary bone marrow stromal cells(BMSCs)after conditional deletion of the Notch transcription factor RBPjκby Cre recombinase.These data indicate that osteocytic Dll4 activates RBPjκ-dependent canonical Notch signaling in BMSCs for their oriented differentiation towards osteoblasts.Additionally,osteocytic Dll4 holds a great potential for angiogenesis in human umbilical vein endothelial cells within modules.Our study reveals that osteocytic Dll4 could be the osteogenic niche determining cell fate towards osteoblasts.This will open a new avenue to overcome the current limitation of poor cell viability and low bioactivity of traditional orthopedic implants.展开更多
Against the dual background of deepening the construction of new liberal arts and implementing the"Double Ten Thousand Plan"for first-class undergraduate courses,local universities urgently need to explore d...Against the dual background of deepening the construction of new liberal arts and implementing the"Double Ten Thousand Plan"for first-class undergraduate courses,local universities urgently need to explore distinctive curriculum construction paths.Based on the requirements of the new liberal arts connotation,this paper constructs a three-dimensional integrated framework of"value guidance,ability driven,and knowledge foundation",and takes the construction of the"Finance"course at Yangtze University as a typical case for research.When systematically analyzing the"Finance"course in the school,a three-dimensional integrated curriculum reform practice is implemented by reshaping the three-level curriculum objectives of"state-society-individual",developing teaching content that integrates"modularization-localization-cutting-edge",using the"O-PRAISE"situational teaching method,and constructing a diversified collaborative evaluation system.A first-class curriculum construction model for local universities has been summarized,which involves five collaborative approaches:"localization"of target positioning,"integration"of content construction,"contextualization"of method implementation,"value-added"evaluation orientation,and"synergy"of resource guarantee.The aim is to provide theoretical paradigms and practical solutions for similar universities to learn from,effectively solving practical difficulties such as the disconnect between value shaping and knowledge transmission,and the mismatch between talent cultivation and local needs in curriculum construction.展开更多
Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, fo...Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.展开更多
The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have hug...The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have huge demands on high integration density and low power consumption.The cross-point configuration or passive array,which offers the smallest footprint of cell size and feasible capability of multi-layer stacking,has received broad attention from the research community.In such array,correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells.This target requires nonlinear I-V characteristics of the memory cell,which can be realized by either adding separate selector or developing implicit build-in nonlinear cells.The performance of a passive array largely depends on the cell nonlinearity,reliability,on/off ratio,line resistance,thermal coupling,etc.This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration.First,the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures.Next,the state of the arts on the development of various selector devices and self-selective cells are presented.Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles.Then,the reliability issues in 3D array are summarized in terms of uniformity,endurance,retention,and disturbance.Subsequently,scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed,and applications of 3D RRAM beyond storage,such as neuromorphic computing and CMOL circuit are discussed later.Summary and outlooks are given in the final.展开更多
In this work,on-chip three-dimensional(3D)photonic integrated optical sources based on active fluorescent polymer waveguide microdisks are proposed for light display application.Fluorescent green and red oligomers wit...In this work,on-chip three-dimensional(3D)photonic integrated optical sources based on active fluorescent polymer waveguide microdisks are proposed for light display application.Fluorescent green and red oligomers with high-efficiency photoluminescence are doped into epoxy crosslinking SU-8 polymer as the waveguide gain medium.The microdisk-based on-chip optically pumping light sources are designed and fabricated using the organic functionalized materials by direct UV written process.The promising stacking dual-microdisk structures with double gain layers could provide white signal light source generated perpendicular to the chip,and green signal light source stimulated in the chip.The approach could realize the monolithically on-chip assembled vertical and horizontal bright emitters.The optical pumping threshold power is obtained as 50 mW with continuous-wave(CW)pumping.The average gain coefficient of a white light source is measured by vertical fiber coupling as 112 dB/W,and that of green light source by horizontal fiber coupling as 137 dB/W,respectively.The rising and falling response time of the on-chip optical sources are 60 and 80μs under modulating pulsed pumping.This technique is very promising for achieving 3D integrated light display application,including photonic circuits and optical information encryption.展开更多
Multilayer frequency selective surfaces(FSSs)have become core components of multi-band communication systems because they possess high selectivity,stability,and out-of-band suppression capabilities.However,interlayer ...Multilayer frequency selective surfaces(FSSs)have become core components of multi-band communication systems because they possess high selectivity,stability,and out-of-band suppression capabilities.However,interlayer reliability problems have negatively affected the manufacture of multilayer FSSs for many years,and these negative impacts are primarily reflected in restrictions in the interlayer bonding strength and the interlayer alignment accuracy.To address these problems,a macroscopic-microscopic cross-scale,multi-material integrated additive manufacturing process was designed during this study.This process,which utilizes electric field-driven(EFD)jet printing and in-situ curing,produced multilayer FSS structures with high-resolution patterning(with a line width of<20μm)and a low alignment error(equal to 0.73%of the periodic dimension).A highly stable micro-interdiffused polyimide(PI)material,which was used for interlayer bonding,was developed by performing trifluoromethyl and fluorenyl side-chain modifications.This material exhibited both extreme environmental adaptability(the PI-based electrodes fabricated using this material exhibited a resistance change rate of less than 5%at 360°C)and a strong interlayer interfacial bonding strength(>3.37 MPa).Using this process and material,a dual-band FSS with passband center frequencies at 14.5 and 60 GHz was designed and fabricated.In addition,the flexibility of the PI material enabled the resultant FSSs to conform to deployable curved surfaces;thus,this material offers a simplified 2D-to-3D fabrication solution for deployable radomes.The proposed binder-free integrated forming process combines environmental sustainability with costeffectiveness;therefore,it serves as a novel strategy for rapid manufacture and performance optimizations of high-frequency communication devices.展开更多
Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhance...Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhanced functionality.Inter-layer vias(ILVs),crucial components of M3D ICs,provide vertical connectivity between layers but are susceptible to manufacturing and operational defects,such as stuck-at faults(SAFs),shorts,and opens,which can compromise system reliability.These challenges necessitate advanced built-in self-test(BIST)methodologies to ensure robust fault detection and localization while minimizing the testing overhead.In this paper,we introduce a novel BIST architecture tailored to efficiently detect ILV defects,particularly in irregularly positioned ILVs,and approximately localize them within clusters,using a walking pattern approach.In the proposed BIST framework,ILVs are grouped according to the probability of fault occurrence,enabling efficient detection of all SAFs and bridging faults(BFs)and most multiple faults within each cluster.This strategy empowers designers to fine-tune fault coverage,localization precision,and test duration to meet specific design requirements.The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters.The method also enhances efficiency in terms of area and hardware utilization,particularly for larger circuit benchmarks.For instance,in the LU32PEENG benchmark,where ILVs are divided into 64 clusters,the power,area,and hardware overheads are minimized to 0.82%,1.03%,and 1.14%,respectively.展开更多
Carbon nanotube field-effect transistors(CNT FETs)have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget to construct monolithic three-dime...Carbon nanotube field-effect transistors(CNT FETs)have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget to construct monolithic three-dimensional(M3D)integrated circuits(ICs),which have been considered a promising tech-nology to meet the demands of high-bandwidth computing and fully func-tional integration.However,the lack of high-quality CNT materials at the upper layer and a low-parasitic interlayer dielectric(ILD)makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance.In this work,we demonstrate a multilayer stackable process for M3D integration of high-performance aligned carbon nanotube(A-CNT)transistors and ICs.A low-κ(-3)interlayer SiO_(2)layer is prepared from spin-on-glass(SOG)through processes with a highest temperature of 220℃,presenting low parasitic capaci-tance between two transistor layers and excellent planarization to offer an ideal surface for the A-CNT and device fabrication process.A high-quality A-CNT film with a carrier mobility of 650 cm 2 V^(-1)s^(-1)is prepared on the ILD layer through a clean transfer process,enabling the upper CNT FETs fabri-cated with a low-temperature process to exhibit high on-state current(1 mAμm^(-1))and peak transconductance(0.98 mSμm^(-1)).The bottom A-CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication.As a result,5-stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100μm 2,representing the fastest and the most compact M3D ICs to date.展开更多
Due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-D and 3-D ICs. In this study,thr...Due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-D and 3-D ICs. In this study,through glass vias(TGVs) are used to implement 3-D inductors for minimal footprint and large quality factor. Using the inductors and parallel plate capacitors, a compact 3-D Wilkinson power divider is designed and analyzed.Compared with some reported power dividers, the proposed TGV-based circuit has an ultra-compact size and excellent electrical performance.展开更多
基金supported by the National Natural Science Foundation of China(52272177,12204010)the Foundation for the Introduction of High-Level Talents of Anhui University(S020118002/097)+1 种基金the University Synergy Innovation Program of Anhui Province(GXXT-2023-066)the Scientific Research Project of Anhui Provincial Higher Education Institution(2023AH040008)。
文摘Flexible electronics face critical challenges in achieving monolithic three-dimensional(3D)integration,including material compatibility,structural stability,and scalable fabrication methods.Inspired by the tactile sensing mechanism of the human skin,we have developed a flexible monolithic 3D-integrated tactile sensing system based on a holey MXene paste,where each vertical one-body unit simultaneously functions as a microsupercapacitor and pressure sensor.The in-plane mesopores of MXene significantly improve ion accessibility,mitigate the self-stacking of nanosheets,and allow the holey MXene to multifunctionally act as a sensing material,an active electrode,and a conductive interconnect,thus drastically reducing the interface mismatch and enhancing the mechanical robustness.Furthermore,we fabricate a large-scale device using a blade-coating and stamping method,which demonstrates excellent mechanical flexibility,low-power consumption,rapid response,and stable long-term operation.As a proof-of-concept application,we integrate our sensing array into a smart access control system,leveraging deep learning to accurately identify users based on their unique pressing behaviors.This study provides a promising approach for designing highly integrated,intelligent,and flexible electronic systems for advanced human-computer interactions and personalized electronics.
基金fundings from the National Natural Science Foundation of China(Nos.62274013 and 92163206)the National Key Research and Development Program of China(No.2023YFB3405600)Science Fund for Creative Research Groups of the National Natural Science Foundation of China(No.12321004)。
文摘Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the evolution of M3D integration from traditional bulk semiconductors to low-dimensional materials like two-dimensioanl(2D)transition metal dichalcogenides(TMDCs)and carbon nanotubes(CNTs).Key applications include logic circuits,static random access memory(SRAM),resistive random access memory(RRAM),sensors,optoelectronics,and artificial intelligence(AI)processing.M3D integration enhances device performance by reducing footprint,improving power efficiency,and alleviating the von Neumann bottleneck.The integration of 2D materials in M3D structures demonstrates significant advancements in terms of scalability,energy efficiency,and functional diversity.Challenges in manufacturing and scaling are discussed,along with prospects for future research directions.Overall,the M3D integration with low-dimensional materials presents a promising pathway for the development of next-generation electronic devices and systems.
基金Project (No. 2009ZX02038) supported by the National Science and Technology Major Project of China
文摘With the development of 3D integration technology, microsystems with vertical interconnects are attracting attention from researchers and industry applications. Basic elements of integrated passive devices （IPDs）, including inductors, capacitors, and resistors, could dramatically save the tbotprint of the system, optimize the form factor, and improve the performance of radio frequency （RF） systems. In this paper, IPDs using thin film built-up technology are introduced, and the design and characterization of coplanar waveguides （CPWs）, inductors, and capacitors are presented.
文摘Polymer insulating through-silicon-vias （TSVs） is an attractive approach for high-performance 3D integration systems. To further demonstrate the polymer insulating TSVs, this paper investigates the thermal stability by measuring the leakage current under bias-temperature condition, studies the thermal stress characteristics with Finite Element Analysis （FEA）, and tries to improve the thermal mechanical reliability of high-density TSVs array by optimizing the geometry parameters of pitch, liner and redistribution layer （RDL）. The electrical measurements show the polymer insulating TSVs can maintain good insulation capability （less than 2x 10TM A） under challenging bias-temperature conditions of 20 V and 200~C, despite the leakage degra- dation observation. The FEA results show that the thermal stress is significantly reduced at the sidewall, but highly concen- trates at the surface, which is the potential location of mechanical failure. And, the analysis results indicate that the polymer insulating TSVs （diameter of 10 μm, depth of 50 μm） array with a pitch of 20 μm, liner thickness of 1 μm and RDL radius of 9 μm has an optimized thermal-mechanical reliability for application.
基金funded by Open Foundation of the State Key Laboratory of Advanced Inorganic Fibers and Composites(Grant No.KF2024SYS02)the Jiangsu Province Special Fund for Carbon Peaking and Carbon Neutrality Technology Innovation(Grant No.BE2022008)the Prioritized Academic Program Development for Higher Education Institutions in Jiangsu.
文摘This study investigates the low-velocity impact and post-impact flexural properties of 3D integrated woven spacer composites,focusing on their orthotropic behavior when tested along two principal directions,i.e.,warp(X-type)and weft(Y-type)directions.The same composite material was tested in these orientations to evaluate the differences in impact resistance and residual bending strength.Specimens were fabricated via vacuum-assisted molding and tested at 2,3,5,and 7 J impact energies using an Instron Ceast 9350 drop-weight impact testing machine,in accordance with ASTM D7136.Post-impact flexural tests were performed using a four-point bending method in accordance with ASTM D7264.The absorbed energy increased from 1.97 to 6.98 J,and the panel damage area ranged from 121 to 361 mm^(2) as impact energy roses.Specimens tested in the weft direction(Y-type)showed greater residual strength(up to 15.83 N)and displacement(up to 0.538 mm)than those tested in the warp direction(X-type).Ultrasonic C-scan imaging revealed localized matrix cracking and fiber failure damage patterns.Results emphasize the directional differences in impact resistance and residual bending properties,highlighting the importance of material orientation in structural applications.This study provides a foundation for utilizing 3D woven spacer composites in lightweight,damage-tolerant structural components.
基金supported by the National Research Foundation of Korea(NRF)funded by the Ministry of Science and ICT(MSIT),South Korea(RS-2024-00421181)financially supported in part by National R&D Program(2021M3H4A3A02086430)through NRF(National Research Foundation of Korea)funded by Ministry of Science and ICT+2 种基金the National Research Council of Science&Technology(NST)grant by the Korea government(MSIT)(No.GTL25021-210)The Inter-University Semiconductor Research Center,Institute of Engineering Research,and Soft Foundry Institute at Seoul National University provided research facilities for this workhe grant by the National Research Foundation of Korea(NSF)supported by the Korea government(MIST)(RS-2025-16903034)。
文摘As silicon-based transistors face fundamental scaling limits,the search for breakthrough alternatives has led to innovations in 3D architectures,heterogeneous integration,and sub-3 nm semiconductor body thicknesses.However,the true effectiveness of these advancements lies in the seamless integration of alternative semiconductors tailored for next-generation transistors.In this review,we highlight key advances that enhance both scalability and switching performance by leveraging emerging semiconductor materials.Among the most promising candidates are 2D van der Waals semiconductors,Mott insulators,and amorphous oxide semiconductors,which offer not only unique electrical properties but also low-power operation and high carrier mobility.Additionally,we explore the synergistic interactions between these novel semiconductors and advanced gate dielectrics,including high-K materials,ferroelectrics,and atomically thin hexagonal boron nitride layers.Beyond introducing these novel material configurations,we address critical challenges such as leakage current and long-term device reliability,which become increasingly crucial as transistors scale down to atomic dimensions.Through concrete examples showcasing the potential of these materials in transistors,we provide key insights into overcoming fundamental obstacles—such as device reliability,scaling down limitations,and extended applications in artificial intelligence—ultimately paving the way for the development of future transistor technologies.
文摘A 3D fan-out packaging method for the integration of 5G communication RF microsystem and antenna is studied.First of all,through the double-sided wiring technology on the glass wafer,the fabrication of 5G antenna array is realized.Then the low power devices such as through silicon via(TSV)transfer chips,filters and antenna tuners are flip-welded on the glass wafer,and the glass wafer is reformed into a wafer permanently bonded with glass and resin by the injection molding process with resin material.Finally,the thinning resin surface leaks out of the TSV transfer chip,the rewiring is carried out on the resin surface,and then the power amplifier,low-noise amplifier,power management and other devices are flip-welded on the resin wafer surface.A ball grid array(BGA)is implanted to form the final package.The loss of the RF transmission line is measured by using the RF millimeter wave probe table.The results show that the RF transmission loss from the chip end to the antenna end in the fan-out package is very small,and it is only 0.26 dB/mm when working in 60 GHz.A slot coupling antenna is designed on the glass wafer.The antenna can operate at 60 GHz and the maximum gain can reach 6 dB within the working bandwidth.This demonstration successfully provides a feasible solution for the 3D fan-out integration of RF microsystem and antenna in 5G communications.
基金Supported by the National High Technology Re-search and Development Programof China(2003AA411011)
文摘Some key issues in supporting collaborative design in product data management（PDM ） system and 3D computer aided design（CAD） system integrated environment are analyzed. The general architecture of the integrated environment is divided into five tiers and employs the transparently integrated mode, with the mode, function calling and information exchanging among independent PDM and CAD processes are carried out via message translation /parse approach. Product layout feature（PLF ） model definition is presented, PLF model is used to represent design intention at the preliminary design phase. The collaborative design methodology employing the PLF model in PDM/3D CAD integrated environment is analyzed. The design methodology can speed up the design process, reduce the investment and improve the product quality.
基金supported by the National Natural Science Foundation of China(Grant No.51901082)the National Postdoctoral Program for Innovative Talents(BX20200137)the National Defense Basic Scientific Research Program of China(JCKY2018110C060)。
文摘Additive manufacturing(AM)is a free-form technology that shows great potential in the integrated creation of three-dimensional(3D)electronics.However,the fabrication of 3D conformal circuits that fulfill the requirements of high service temperature,high conductivity and high resolution remains a challenge.In this paper,a hybrid AM method combining the fused deposition modeling(FDM)and hydrophobic treatment assisted laser activation metallization(LAM)was proposed for manufacturing the polyetheretherketone(PEEK)-based 3D electronics,by which the conformal copper patterns were deposited on the 3D-printed PEEK parts,and the adhesion between them reached the 5B high level.Moreover,the 3D components could support the thermal cycling test from-55℃ to 125℃ for more than 100 cycles.Particularly,the application of a hydrophobic coating on the FDM-printed PEEK before LAM can promote an ideal catalytic selectivity on its surface,not affected by the inevitable printing borders and pores in the FDM-printed parts,then making the resolution of the electroless plated copper lines improved significantly.In consequence,Cu lines with width and spacing of only60μm and 100μm were obtained on both as-printed and after-polished PEEK substrates.Finally,the potential of this technique to fabricate 3D conformal electronics was demonstrated.
基金The National Natural Science Foundation of China(No.61674048,61574052,61474036,61371025)the Project of Anhui Institute of Economics and Management(No.YJKT1417T01)
文摘In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.
基金supported by the National Natural Science Foundation of China(Grant nos.52272201,52072136,52172229,52302303,and 51972257)Yanchang Petroleum-WHUT Joint Program(yc-whlg-2022ky-05)+1 种基金the State Key Laboratory of Advanced Technology for Materials Synthesis and Processing(Wuhan University of Technology,2022-KF-20)Fundamental Research Funds for the Central Universities(2023IVA106)for financial support
文摘FeS_(2)cathode is promising for all-solid-state lithium batteries due to its ultra-high capacity,low cost,and environmental friendliness.However,the poor performances,induced by limited electrode-electrolyte interface,severe volume expansion,and polysulfide shuttle,hinder the application of FeS_(2)in all-solid-state lithium batteries.Herein,an integrated 3D FeS_(2)electrode with full infiltration of Li6PS5Cl sulfide electrolytes is designed to address these challenges.Such a 3D integrated design not only achieves intimate and maximized interfacial contact between electrode and sulfide electrolytes,but also effectively buffers the inner volume change of FeS_(2)and completely eliminates the polysulfide shuttle through direct solid-solid conversion of Li2S/S.Besides,the vertical 3D arrays guarantee direct electron transport channels and horizontally shortened ion diffusion paths,endowing the integrated electrode with a remarkably reduced interfacial impedance and enhanced reaction kinetics.Benefiting from these synergies,the integrated all-solid-state lithium battery exhibits the largest reversible capacity(667 mAh g^(-1)),best rate performance,and highest capacity retention of 82%over 500 cycles at 0.1 C compared to both a liquid battery and non-integrated all-solid-state lithium battery.The cycling performance is among the best reported for FeS_(2)-based all-solid-state lithium batteries.This work presents an innovative synergistic strategy for designing long-cycling high-energy all-solid-state lithium batteries,which can be readily applied to other battery systems,such as lithium-sulfur batteries.
基金the National Natural Science Foundation of China(Nos.U1601220,82072450,and 81672118)Chongqing Science and Technology Commission-Basic Science and Frontier Technology Key Project(No.cstc2015jcyjBX0119)Chongqing Medical University Intelligent Medicine Research Project(No.ZHYX202115).
文摘Since 3D printed hard materials could match the shape of bone,cell survival and fate determination towards osteoblasts in such materials have become a popular research target.In this study,a scaffold of hardmaterial for 3D fabrication was designed to regulate developmental signal(Notch)transduction guiding osteoblast differentiation.We established a polycaprolactone(PCL)and cell-integrated 3D printing system(PCI3D)to reciprocally print the beams of PCL and cell-laden hydrogel for a module.This PCI3D module holds good cell viability of over 87%,whereas cells show about sixfold proliferation in a 7-day culture.The osteocytic MLO-Y4 was engineered to overexpress Notch ligand Dll4,making up 25%after mixing with 75%stromal cells in the PCI3D module.Osteocytic Dll4,unlike other delta-like family members such as Dll1 or Dll3,promotes osteoblast differentiation and themineralization of primary mouse and a cell line of bone marrow stromal cells when cultured in a PCI3D module for up to 28 days.Mechanistically,osteocytic Dll4 could not promote osteogenic differentiation of the primary bone marrow stromal cells(BMSCs)after conditional deletion of the Notch transcription factor RBPjκby Cre recombinase.These data indicate that osteocytic Dll4 activates RBPjκ-dependent canonical Notch signaling in BMSCs for their oriented differentiation towards osteoblasts.Additionally,osteocytic Dll4 holds a great potential for angiogenesis in human umbilical vein endothelial cells within modules.Our study reveals that osteocytic Dll4 could be the osteogenic niche determining cell fate towards osteoblasts.This will open a new avenue to overcome the current limitation of poor cell viability and low bioactivity of traditional orthopedic implants.
基金Supported by Yangtze University School-level Teaching Research Project(JY2021038,JY2022009,JY2024059)。
文摘Against the dual background of deepening the construction of new liberal arts and implementing the"Double Ten Thousand Plan"for first-class undergraduate courses,local universities urgently need to explore distinctive curriculum construction paths.Based on the requirements of the new liberal arts connotation,this paper constructs a three-dimensional integrated framework of"value guidance,ability driven,and knowledge foundation",and takes the construction of the"Finance"course at Yangtze University as a typical case for research.When systematically analyzing the"Finance"course in the school,a three-dimensional integrated curriculum reform practice is implemented by reshaping the three-level curriculum objectives of"state-society-individual",developing teaching content that integrates"modularization-localization-cutting-edge",using the"O-PRAISE"situational teaching method,and constructing a diversified collaborative evaluation system.A first-class curriculum construction model for local universities has been summarized,which involves five collaborative approaches:"localization"of target positioning,"integration"of content construction,"contextualization"of method implementation,"value-added"evaluation orientation,and"synergy"of resource guarantee.The aim is to provide theoretical paradigms and practical solutions for similar universities to learn from,effectively solving practical difficulties such as the disconnect between value shaping and knowledge transmission,and the mismatch between talent cultivation and local needs in curriculum construction.
基金Sponsored by the National Natural Science Foundation of China(No.61271149)
文摘Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.
基金the National Key R&D Program of China(Grant Nos.2018YFB0407501 and 2016YFA0201800)the National Natural Science Foundation of China(Grant Nos.61804173,61922083,61804167,61904200,and 61821091)the fourth China Association for Science and Technology Youth Talent Support Project(Grant No.2019QNRC001).
文摘The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have huge demands on high integration density and low power consumption.The cross-point configuration or passive array,which offers the smallest footprint of cell size and feasible capability of multi-layer stacking,has received broad attention from the research community.In such array,correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells.This target requires nonlinear I-V characteristics of the memory cell,which can be realized by either adding separate selector or developing implicit build-in nonlinear cells.The performance of a passive array largely depends on the cell nonlinearity,reliability,on/off ratio,line resistance,thermal coupling,etc.This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration.First,the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures.Next,the state of the arts on the development of various selector devices and self-selective cells are presented.Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles.Then,the reliability issues in 3D array are summarized in terms of uniformity,endurance,retention,and disturbance.Subsequently,scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed,and applications of 3D RRAM beyond storage,such as neuromorphic computing and CMOL circuit are discussed later.Summary and outlooks are given in the final.
基金National Key Research and Development(R&D)Program of China(2019YFB2203001)National Natural Science Foundation of China(NSFC,No.62171195).
文摘In this work,on-chip three-dimensional(3D)photonic integrated optical sources based on active fluorescent polymer waveguide microdisks are proposed for light display application.Fluorescent green and red oligomers with high-efficiency photoluminescence are doped into epoxy crosslinking SU-8 polymer as the waveguide gain medium.The microdisk-based on-chip optically pumping light sources are designed and fabricated using the organic functionalized materials by direct UV written process.The promising stacking dual-microdisk structures with double gain layers could provide white signal light source generated perpendicular to the chip,and green signal light source stimulated in the chip.The approach could realize the monolithically on-chip assembled vertical and horizontal bright emitters.The optical pumping threshold power is obtained as 50 mW with continuous-wave(CW)pumping.The average gain coefficient of a white light source is measured by vertical fiber coupling as 112 dB/W,and that of green light source by horizontal fiber coupling as 137 dB/W,respectively.The rising and falling response time of the on-chip optical sources are 60 and 80μs under modulating pulsed pumping.This technique is very promising for achieving 3D integrated light display application,including photonic circuits and optical information encryption.
基金supported by the National Natural Science Foundation of China(Grant Nos.52375348,52175331)the National Natural Science Foundation of Shandong Province(Grant No.ZR2022ME014)the Taishan Scholars Program of Shandong Province(Grant No.tsqn202408219)。
文摘Multilayer frequency selective surfaces(FSSs)have become core components of multi-band communication systems because they possess high selectivity,stability,and out-of-band suppression capabilities.However,interlayer reliability problems have negatively affected the manufacture of multilayer FSSs for many years,and these negative impacts are primarily reflected in restrictions in the interlayer bonding strength and the interlayer alignment accuracy.To address these problems,a macroscopic-microscopic cross-scale,multi-material integrated additive manufacturing process was designed during this study.This process,which utilizes electric field-driven(EFD)jet printing and in-situ curing,produced multilayer FSS structures with high-resolution patterning(with a line width of<20μm)and a low alignment error(equal to 0.73%of the periodic dimension).A highly stable micro-interdiffused polyimide(PI)material,which was used for interlayer bonding,was developed by performing trifluoromethyl and fluorenyl side-chain modifications.This material exhibited both extreme environmental adaptability(the PI-based electrodes fabricated using this material exhibited a resistance change rate of less than 5%at 360°C)and a strong interlayer interfacial bonding strength(>3.37 MPa).Using this process and material,a dual-band FSS with passband center frequencies at 14.5 and 60 GHz was designed and fabricated.In addition,the flexibility of the PI material enabled the resultant FSSs to conform to deployable curved surfaces;thus,this material offers a simplified 2D-to-3D fabrication solution for deployable radomes.The proposed binder-free integrated forming process combines environmental sustainability with costeffectiveness;therefore,it serves as a novel strategy for rapid manufacture and performance optimizations of high-frequency communication devices.
文摘Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhanced functionality.Inter-layer vias(ILVs),crucial components of M3D ICs,provide vertical connectivity between layers but are susceptible to manufacturing and operational defects,such as stuck-at faults(SAFs),shorts,and opens,which can compromise system reliability.These challenges necessitate advanced built-in self-test(BIST)methodologies to ensure robust fault detection and localization while minimizing the testing overhead.In this paper,we introduce a novel BIST architecture tailored to efficiently detect ILV defects,particularly in irregularly positioned ILVs,and approximately localize them within clusters,using a walking pattern approach.In the proposed BIST framework,ILVs are grouped according to the probability of fault occurrence,enabling efficient detection of all SAFs and bridging faults(BFs)and most multiple faults within each cluster.This strategy empowers designers to fine-tune fault coverage,localization precision,and test duration to meet specific design requirements.The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters.The method also enhances efficiency in terms of area and hardware utilization,particularly for larger circuit benchmarks.For instance,in the LU32PEENG benchmark,where ILVs are divided into 64 clusters,the power,area,and hardware overheads are minimized to 0.82%,1.03%,and 1.14%,respectively.
基金National Key Research&Development Program,Grant/Award Number:2022YFB4401601Natural Science Foundation of China,Grant/Award Number:62225101Beijing Municipal Science and Technology Commission,Grant/Award Number:Z191100007019001-3。
文摘Carbon nanotube field-effect transistors(CNT FETs)have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget to construct monolithic three-dimensional(M3D)integrated circuits(ICs),which have been considered a promising tech-nology to meet the demands of high-bandwidth computing and fully func-tional integration.However,the lack of high-quality CNT materials at the upper layer and a low-parasitic interlayer dielectric(ILD)makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance.In this work,we demonstrate a multilayer stackable process for M3D integration of high-performance aligned carbon nanotube(A-CNT)transistors and ICs.A low-κ(-3)interlayer SiO_(2)layer is prepared from spin-on-glass(SOG)through processes with a highest temperature of 220℃,presenting low parasitic capaci-tance between two transistor layers and excellent planarization to offer an ideal surface for the A-CNT and device fabrication process.A high-quality A-CNT film with a carrier mobility of 650 cm 2 V^(-1)s^(-1)is prepared on the ILD layer through a clean transfer process,enabling the upper CNT FETs fabri-cated with a low-temperature process to exhibit high on-state current(1 mAμm^(-1))and peak transconductance(0.98 mSμm^(-1)).The bottom A-CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication.As a result,5-stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100μm 2,representing the fastest and the most compact M3D ICs to date.
基金Projected supported by the National Natural Science Foundation of China(Nos.61771268,61571248,U1709218)the Science and Technology Fund of Zhejiang Province(No.2015C31090)+1 种基金the Natural Science Foundation of Zhejiang(No.LY17F040002)the K.C.Wong Magna Fund in Ningbo University
文摘Due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-D and 3-D ICs. In this study,through glass vias(TGVs) are used to implement 3-D inductors for minimal footprint and large quality factor. Using the inductors and parallel plate capacitors, a compact 3-D Wilkinson power divider is designed and analyzed.Compared with some reported power dividers, the proposed TGV-based circuit has an ultra-compact size and excellent electrical performance.
