In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is bu...In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.展开更多
Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhance...Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhanced functionality.Inter-layer vias(ILVs),crucial components of M3D ICs,provide vertical connectivity between layers but are susceptible to manufacturing and operational defects,such as stuck-at faults(SAFs),shorts,and opens,which can compromise system reliability.These challenges necessitate advanced built-in self-test(BIST)methodologies to ensure robust fault detection and localization while minimizing the testing overhead.In this paper,we introduce a novel BIST architecture tailored to efficiently detect ILV defects,particularly in irregularly positioned ILVs,and approximately localize them within clusters,using a walking pattern approach.In the proposed BIST framework,ILVs are grouped according to the probability of fault occurrence,enabling efficient detection of all SAFs and bridging faults(BFs)and most multiple faults within each cluster.This strategy empowers designers to fine-tune fault coverage,localization precision,and test duration to meet specific design requirements.The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters.The method also enhances efficiency in terms of area and hardware utilization,particularly for larger circuit benchmarks.For instance,in the LU32PEENG benchmark,where ILVs are divided into 64 clusters,the power,area,and hardware overheads are minimized to 0.82%,1.03%,and 1.14%,respectively.展开更多
To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The c...To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys＇s Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from l0 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.展开更多
Metallurgical challenges in controlling the microstructural stability of Cu and solder microbumps in 3D IC packaging technol-ogy are discussed. Using uni-directional 【111】 oriented nanotwinned Cu, the controlled gro...Metallurgical challenges in controlling the microstructural stability of Cu and solder microbumps in 3D IC packaging technol-ogy are discussed. Using uni-directional 【111】 oriented nanotwinned Cu, the controlled growth of oriented Cu6Sn5 on the nanotwinned Cu and its transformation to Cu3Sn without Kirkendall voids have been achieved. In order to join a stack of Si chips into a 3D device, multiple reflows of solder microbumps may be required; we consider localized heating to do so by the use of self-sustained explosive reaction in multi-layered Al/Ni thin films of nano thickness. It avoids re-melting of those solder joints which have been formed already in the 3D stacking structure.展开更多
基金The National Natural Science Foundation of China(No.61674048,61574052,61474036,61371025)the Project of Anhui Institute of Economics and Management(No.YJKT1417T01)
文摘In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.
文摘Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhanced functionality.Inter-layer vias(ILVs),crucial components of M3D ICs,provide vertical connectivity between layers but are susceptible to manufacturing and operational defects,such as stuck-at faults(SAFs),shorts,and opens,which can compromise system reliability.These challenges necessitate advanced built-in self-test(BIST)methodologies to ensure robust fault detection and localization while minimizing the testing overhead.In this paper,we introduce a novel BIST architecture tailored to efficiently detect ILV defects,particularly in irregularly positioned ILVs,and approximately localize them within clusters,using a walking pattern approach.In the proposed BIST framework,ILVs are grouped according to the probability of fault occurrence,enabling efficient detection of all SAFs and bridging faults(BFs)and most multiple faults within each cluster.This strategy empowers designers to fine-tune fault coverage,localization precision,and test duration to meet specific design requirements.The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters.The method also enhances efficiency in terms of area and hardware utilization,particularly for larger circuit benchmarks.For instance,in the LU32PEENG benchmark,where ILVs are divided into 64 clusters,the power,area,and hardware overheads are minimized to 0.82%,1.03%,and 1.14%,respectively.
基金supported by the National Natural Science Foundation of China(No.61422402)the Tsinghua University Initiative Scientific Research Program
文摘To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys＇s Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from l0 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.
文摘Metallurgical challenges in controlling the microstructural stability of Cu and solder microbumps in 3D IC packaging technol-ogy are discussed. Using uni-directional 【111】 oriented nanotwinned Cu, the controlled growth of oriented Cu6Sn5 on the nanotwinned Cu and its transformation to Cu3Sn without Kirkendall voids have been achieved. In order to join a stack of Si chips into a 3D device, multiple reflows of solder microbumps may be required; we consider localized heating to do so by the use of self-sustained explosive reaction in multi-layered Al/Ni thin films of nano thickness. It avoids re-melting of those solder joints which have been formed already in the 3D stacking structure.
