According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barrier...According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.展开更多
This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down tran...This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.展开更多
Low stress polishing is required for the manufacture of advanced integrated circuits(IC) with node sizes of 45 nm and smaller.However,the CMP community achieved the low stress by reducing the down force that press the...Low stress polishing is required for the manufacture of advanced integrated circuits(IC) with node sizes of 45 nm and smaller.However,the CMP community achieved the low stress by reducing the down force that press the wafer against a rotating pad.The reduced down force also decrease the removal rate of the wafer. As a result,the productivity suffers.In order to cope with this problem,an electrical potential is applied to the copper layer during polishing,in this case,the chemical oxidation is accelearated and hence the removal rate. Alternatively,the rotating pad must be softened to minimize the defects of wafers caused by CMP. In this research,we report a simpler solution to achieve low stress polishing without investing in new equipment and in developing new pad materials.The conventional CMP is proceeded by dressing the pad with a PCD dresser that can form 10×more asperities on the pad surface.The fluffy surface can then polish delicate IC without using the brutal force.As a result,the removal rate of wafers can be maintained without causing defectivity on the IC layer.展开更多
文摘According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.
文摘This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.
文摘Low stress polishing is required for the manufacture of advanced integrated circuits(IC) with node sizes of 45 nm and smaller.However,the CMP community achieved the low stress by reducing the down force that press the wafer against a rotating pad.The reduced down force also decrease the removal rate of the wafer. As a result,the productivity suffers.In order to cope with this problem,an electrical potential is applied to the copper layer during polishing,in this case,the chemical oxidation is accelearated and hence the removal rate. Alternatively,the rotating pad must be softened to minimize the defects of wafers caused by CMP. In this research,we report a simpler solution to achieve low stress polishing without investing in new equipment and in developing new pad materials.The conventional CMP is proceeded by dressing the pad with a PCD dresser that can form 10×more asperities on the pad surface.The fluffy surface can then polish delicate IC without using the brutal force.As a result,the removal rate of wafers can be maintained without causing defectivity on the IC layer.
