Traditional intensity modulated two-level electrical time-division multiplexing （ETDM） transmission systems working at 100 -112 Gbit/s were investigated. The complete ETDM systems based on monolithically integrated ...Traditional intensity modulated two-level electrical time-division multiplexing （ETDM） transmission systems working at 100 -112 Gbit/s were investigated. The complete ETDM systems based on monolithically integrated transmitter and receiver modules were demonstrated with biterror-rate （BER） performance of 10-s at 107 Gbit/s, and near error-free standard forward error correction （FEC） threshold （2 × 10 -3） at 112 Gbit/s. The experiment results showed that directly modulated high-speed ETDM transmission systems with the symbol rates at 100 Gbaud and beyond were promising candidate for cost-effective 100 GbE applications and might be a preform of the next generation of Terabit/s Ethernet.展开更多
This paper presents a transmit physical coding sublayer（PCS） circuit for 100 G Ethernet. Based on the4×25 Gb/s architecture according to the IEEE P802.3ba and IEEE P802.3bm-（TM）/D1.1 standards, this PCS circu...This paper presents a transmit physical coding sublayer（PCS） circuit for 100 G Ethernet. Based on the4×25 Gb/s architecture according to the IEEE P802.3ba and IEEE P802.3bm-（TM）/D1.1 standards, this PCS circuit is designed using a semi-custom design method and consists of 4 modules including 64B/66 B encoder, scrambler,multiple lanes distribution and 66 ： 8 gearbox. By using the pipeline structure and several optimization techniques,the working speed of the circuit is increased significantly. The parallel scrambling combined with logic optimization also improve the performance. In addition, a kind of phase-independent structure is employed in the design of the gearbox to ensure it can work stably and reliably at high frequency. This PCS circuit has been fabricated based on0.18μm CMOS technology and the total area is 1.7×1.7 mm^2. Measured results show that the circuit can work properly at 100 Gb/s and the power consumption is about 284 m W with a 1.8 V supply.展开更多
A 25 Gbit/s clock and data recovery （CDR） circuit with 1：2 demultiplexer for 100 Gbit/s Ethemet （100 GbE） optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company （TSMC...A 25 Gbit/s clock and data recovery （CDR） circuit with 1：2 demultiplexer for 100 Gbit/s Ethemet （100 GbE） optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company （TSMC） 65nm complementary metal-oxide-semiconductor （CMOS） technology. A novel quadrature voltage-controlled-oscillator （QVCO） structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 231 - 1 pseudorandom bit sequence （PRBS） input. For 1.2 V voltage supply, the CDR circuit consumes 92 mW （excluding output buffers）.展开更多
基金Supported by the European Committee6th Research Framework Program in the Project HECTO
文摘Traditional intensity modulated two-level electrical time-division multiplexing （ETDM） transmission systems working at 100 -112 Gbit/s were investigated. The complete ETDM systems based on monolithically integrated transmitter and receiver modules were demonstrated with biterror-rate （BER） performance of 10-s at 107 Gbit/s, and near error-free standard forward error correction （FEC） threshold （2 × 10 -3） at 112 Gbit/s. The experiment results showed that directly modulated high-speed ETDM transmission systems with the symbol rates at 100 Gbaud and beyond were promising candidate for cost-effective 100 GbE applications and might be a preform of the next generation of Terabit/s Ethernet.
基金Project supported by the National Natural Science Foundation of China(No.6504000129)the National Basic Research Program of China(No.6504000052)
文摘This paper presents a transmit physical coding sublayer（PCS） circuit for 100 G Ethernet. Based on the4×25 Gb/s architecture according to the IEEE P802.3ba and IEEE P802.3bm-（TM）/D1.1 standards, this PCS circuit is designed using a semi-custom design method and consists of 4 modules including 64B/66 B encoder, scrambler,multiple lanes distribution and 66 ： 8 gearbox. By using the pipeline structure and several optimization techniques,the working speed of the circuit is increased significantly. The parallel scrambling combined with logic optimization also improve the performance. In addition, a kind of phase-independent structure is employed in the design of the gearbox to ensure it can work stably and reliably at high frequency. This PCS circuit has been fabricated based on0.18μm CMOS technology and the total area is 1.7×1.7 mm^2. Measured results show that the circuit can work properly at 100 Gb/s and the power consumption is about 284 m W with a 1.8 V supply.
基金supported by the Communication Systems Project of Jiangsu Department (JHB04010)the National Natural Science Foundation of China (60976029)
文摘A 25 Gbit/s clock and data recovery （CDR） circuit with 1：2 demultiplexer for 100 Gbit/s Ethemet （100 GbE） optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company （TSMC） 65nm complementary metal-oxide-semiconductor （CMOS） technology. A novel quadrature voltage-controlled-oscillator （QVCO） structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 231 - 1 pseudorandom bit sequence （PRBS） input. For 1.2 V voltage supply, the CDR circuit consumes 92 mW （excluding output buffers）.
