This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter （ADC） based on an improved 1.5bit/stage architecture. The ADC achieves a peak signal-to-noise-and-distortion ratio （SNDR） of 57dB and ...This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter （ADC） based on an improved 1.5bit/stage architecture. The ADC achieves a peak signal-to-noise-and-distortion ratio （SNDR） of 57dB and maintains 51dB up to 57MHz, the Nyquist frequency for a clock rate of 100Msample/s. The differential non-linearity （DNL） and integral non-linearity （INL） are typically measured as 0.3LSB and 1.0LSB, respectively. The ADC is implemented in a 0.18μm mixed-signal CMOS technology and occupies 0.76mm^2.展开更多
Currently, 1 bit or 2 bit signal quantization is widely used in satellite navigation software receivers. The bit-wise parallel algorithm has been proposed for 1 bit and 2 bit signal quantization, which performs correl...Currently, 1 bit or 2 bit signal quantization is widely used in satellite navigation software receivers. The bit-wise parallel algorithm has been proposed for 1 bit and 2 bit signal quantization, which performs correlation with high efficiency. In order to improve the performance of the correlator, this paper proposes a new 1.5 bit quantization method. Theoretical analyses are made from the aspects of complexity and quantization loss, and performance comparison between 1.5 bit quantization correlator and traditional correlators is discussed. The results show that the 1.5 bit quantization algorithm can save about 30 percent complexity under similar quantization loss, reduce more than 0.5 dB signal noise ratio（SNR） loss under similar complexity. It shows great performance improvement for correlators of satellite navigation software receivers.展开更多
基金supported by the Research and Development Fund for the Applied Materials of Shanghai City(No.07SA16)~~
文摘This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter （ADC） based on an improved 1.5bit/stage architecture. The ADC achieves a peak signal-to-noise-and-distortion ratio （SNDR） of 57dB and maintains 51dB up to 57MHz, the Nyquist frequency for a clock rate of 100Msample/s. The differential non-linearity （DNL） and integral non-linearity （INL） are typically measured as 0.3LSB and 1.0LSB, respectively. The ADC is implemented in a 0.18μm mixed-signal CMOS technology and occupies 0.76mm^2.
基金supported by the National Natural Science Foundation of China(61101076413741376147017)
文摘Currently, 1 bit or 2 bit signal quantization is widely used in satellite navigation software receivers. The bit-wise parallel algorithm has been proposed for 1 bit and 2 bit signal quantization, which performs correlation with high efficiency. In order to improve the performance of the correlator, this paper proposes a new 1.5 bit quantization method. Theoretical analyses are made from the aspects of complexity and quantization loss, and performance comparison between 1.5 bit quantization correlator and traditional correlators is discussed. The results show that the 1.5 bit quantization algorithm can save about 30 percent complexity under similar quantization loss, reduce more than 0.5 dB signal noise ratio（SNR） loss under similar complexity. It shows great performance improvement for correlators of satellite navigation software receivers.
